|Citizenship||American (formerly Iranian)|
|Projects||CMOS-5X, IBM RoadRunner,|
|Significant advance||CMOS, STI|
|Awards||IBM Fellow, J J Ebers Award, IEEE Andrew S. Grove Award|
Bijan Davari is an Iranian-American engineer. He is an IBM Fellow and Vice President at IBM Thomas J Watson Research Center, Yorktown Hts, NY. His pioneering work in the miniaturization of semiconductor devices changed the world of computing.His research led to the first generation of voltage-scaled deep-submicron CMOS with sufficient performance to totally replace bipolar technology in IBM mainframes and enable new high-performance UNIX servers. He is credited with leading IBM into the use of copper and silicon on insulator before its rivals. He is a member of the U.S. National Academy of Engineers and is known for his seminal contributions to the field of CMOS technology. He is an IEEE Fellow, recipient of the J J Ebers Award in 2005 and IEEE Andrew S. Grove Award in 2010. At the present time, he leads the Next Generation Systems Area of research.
Bijan Davari was born in Tehran, Iran, in 1954.He received his bachelor's degree in electrical engineering from Sharif University of Technology, Tehran, Iran, and his master's degree from Rensselaer Polytechnic Institute (RPI). He received his doctorate from RPI as well with a thesis on the interface behavior of semiconductor devices, and joined IBM Thomas J Watson Research Center in 1984.
At IBM, Davari worked on ways to improve MOSFET (metal-oxide-semiconductor field-effect transistor)and CMOS (complementary metal-oxide-semiconductor) technology, which provides the basis for much of today's semiconductor processing. In 1985, Davari began the task of defining IBM's next generation of CMOS integrated circuits, which came to be called CMOS-5X. He led the research efforts that produced the first generation of high-performance, low voltage deep submicron CMOS technology. CMOS-5X served as the basis for the PowerPC® 601+ and several other microprocessors, including those used in IBM System/390 servers.
Davari defined the roadmap for technology and voltage scaling for IBM nm regime. This technology led to several generations of high-performance, low-voltage and low-power CMOS technologies that enabled servers, portable computers and battery powered handheld devices.which influenced the CMOS roadmap for the industry down to 70
Davari and his team at IBM also demonstrated the first shallow trench isolation (STI) process.STI helps prevent electrical current leakage between semiconductor devices on an integrated circuit. STI process was first used in IBM's 0.5-micrometer technology node for high-performance CMOS logic and in 16-Megabit dynamic RAM. It was eventually used widely throughout the industry.
In 1987, Davari led an IBM research team that demonstrated the first MOSFET with 10 nanometer gate oxide thickness, using tungsten-gate technology. nm channel lengths.In 1988, he led an IBM team that demonstrated high-performance dual-gate CMOS devices with 180 nm to 250
Davari was one of the leaders in the Cell Broadband Engine work at IBM, which was used to build the first Cell-based supercomputer, IBM Roadrunner. In 2008, the Roadrunner supercomputer was the first to break the petaflop barrier,reaching a processing speed of 1.026 petaflops.
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of insulated-gate field-effect transistor (IGFET) that is fabricated by the controlled oxidation of a semiconductor, typically silicon. The voltage of the covered gate determines the electrical conductivity of the device; this ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in November 1959. It is the basic building block of modern electronics, and the most frequently manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.
N-type metal-oxide-semiconductor logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off, triode, saturation, and velocity saturation.
Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.
In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS technology.
The J. J. Ebers Award was established in 1971 to foster progress in electron devices. It commemorates Jewell James Ebers, whose contributions, particularly to transistors, shaped the understanding and technology of electron devices. It is presented annually to one or more individuals who have made either a single or a series of contributions of recognized scientific, economic, or social significance in the broad field of electron devices. The recipient is awarded a certificate and check for $5,000, presented at the International Electron Devices Meeting.
Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.
The 130 nm process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 2001–2002 timeframe, by leading semiconductor companies like Fujitsu, IBM, Intel, Texas Instruments, and TSMC.
The 180 nm process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 1998–2000 timeframe by leading semiconductor companies, starting with TSMC and Fujitsu, then followed by Sony, Toshiba, Intel, AMD, Texas Instruments and IBM.
A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a MOSFET that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are the FinFET and the GAAFET, which are non-planar transistors, or 3D transistors.
Ghavam G. Shahidi is an Iranian-American electrical engineer and IBM Fellow. He is the director of Silicon Technology at the IBM Thomas J Watson Research Center. He is best known for his pioneering work in silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) technology since the late 1980s.
The 250 nm process refers to a level of MOSFET (CMOS) semiconductor process technology that was commercialized by semiconductor manufacturers around the 1996–1998 timeframe.
The 800 nm process refers to the level of MOSFET semiconductor fabrication process technology that was reached around the 1987–1990 timeframe, by leading semiconductor companies like NTT, NEC, Toshiba, IBM, Hitachi, Matsushita, Mitsubishi Electric and Intel.
The 600 nm process refers to the level of CMOS (MOSFET) semiconductor fabrication process technology that was commercialized around the 1990–1995 timeframe, by leading semiconductor companies like Mitsubishi Electric, Toshiba, NEC, Intel and IBM.
Nanocircuits are electrical circuits operating on the nanometer scale. This is well into the quantum realm, where quantum mechanical effects become very important. One nanometer is equal to 10−9 meters or a row of 10 hydrogen atoms. With such progressively smaller circuits, more can be fitted on a computer chip. This allows faster and more complex functions using less power. Nanocircuits are composed of three different fundamental components. These are transistors, interconnections, and architecture, all fabricated on the nanometer scale.
The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET from the underlying source and drain terminals as well as the conductive channel that connects source and drain when the transistor is turned on. Gate oxide is formed by thermal oxidation of the silicon of the channel to form a thin insulating layer of silicon dioxide. The insulating silicon dioxide layer is formed through a process of self-limiting oxidation, which is described by the Deal-Grove model. A conductive gate material is subsequently deposited over the gate oxide to form the transistor. The gate oxide serves as the dielectric layer so that the gate can sustain as high as 1 to 5 MV/cm transverse electric field in order to strongly modulate the conductance of the channel.
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm.
In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5-nanometre MOSFET technology node. As of 2019, Samsung and TSMC have announced plans to put a 3 nm semiconductor node into commercial production. It is based on GAAFET technology, a type of multi-gate MOSFET technology.