# CMOS

Last updated

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET (metal–oxide–semiconductor field-effect transistor) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. [1] CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication.

## Contents

Mohamed M. Atalla and Dawon Kahng invented the MOSFET at Bell Labs in 1959, and then demonstrated the PMOS (p-type MOS) and NMOS (n-type MOS) fabrication processes in 1960. These processes were later combined and adapted into the complementary MOS (CMOS) process by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. RCA commercialized the technology with the trademark "COS-MOS" in the late 1960s, forcing other manufacturers to find another name, leading to "CMOS" becoming the standard name for the technology by the early 1970s. CMOS eventually overtook NMOS as the dominant MOSFET fabrication process for very large-scale integration (VLSI) chips in the 1980s, and has since remained the standard fabrication process for MOSFET semiconductor devices in VLSI chips. As of 2011, 99% of IC chips, including most digital, analog and mixed-signal ICs, are fabricated using CMOS technology. [2]

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. [3] Since one transistor of the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, like NMOS logic or transistor–transistor logic (TTL), which normally have some standing current even when not changing state. These characteristics allow CMOS to integrate a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most widely used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of MOS field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-κ dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and smaller sizes. [4]

## Technical details

"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes. [5] CMOS logic consumes over 7 times less power than NMOS logic, [6] and about 100,000 times less power than bipolar transistor-transistor logic (TTL). [7] [8]

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistor (MOSFETs) to implement logic gates and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of silicon of between 10 and 400 mm2.

CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).

## History

The MOSFET (metal-oxide-semiconductor field-effect transistor, or MOS transistor) was invented by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959. There were originally two types of MOSFET fabrication processes, PMOS (p-type MOS) and NMOS (n-type MOS). [9] Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices with a 20 μm process in 1960. [10] While the MOSFET was initially overlooked and ignored by Bell Labs in favour of bipolar transistors, [10] the MOSFET invention generated significant interest at Fairchild Semiconductor. [9] Base on Atalla's work, [11] Chih-Tang Sah introduced MOS technology to Fairchild with his MOS-controlled tetrode fabricated in late 1960. [9]

A new type of MOSFET logic combining both the PMOS and NMOS processes was developed, called complementary MOS (CMOS), by Chih-Tang Sah and Frank Wanlass at Fairchild. In February 1963, they published the invention in a research paper. [12] [13] Wanlass later filed US patent 3,356,858 for CMOS circuitry in June 1963, and it was granted in 1967. In both the research paper and the patent, the fabrication of CMOS devices was outlined, on the basis of thermal oxidation of a silicon substrate to yield a layer of silicon dioxide located between the drain contact and the source contact. [14] [13]

CMOS was commercialised by RCA in the late 1960s. RCA adopted CMOS for the design of integrated circuits (ICs), developing CMOS circuits for an Air Force computer in 1965 and then a 288-bit CMOS SRAM memory chip in 1968. [12] RCA also used CMOS for its 4000-series integrated circuits in 1968, starting with a 20  μm semiconductor manufacturing process before gradually scaling to a 10 μm process over the next several years. [15]

CMOS technology was initially overlooked by the American semiconductor industry in favour of NMOS, which was more powerful at the time. However, CMOS was quickly adopted and further advanced by Japanese semiconductor manufacturers due to its low power consumption, leading to the rise of the Japanese semiconductor industry. [16] Toshiba developed C²MOS (Clocked CMOS), a circuit technology with lower power consumption and faster operating speed than ordinary CMOS, in 1969. Toshiba used its C²MOS technology to develop a large-scale integration (LSI) chip for Sharp's Elsi Mini LED pocket calculator, developed in 1971 and released in 1972. [17] Suwa Seikosha (now Seiko Epson) began developing a CMOS IC chip for a Seiko quartz watch in 1969, and began mass-production with the launch of the Seiko Analog Quartz 38SQW watch in 1971. [18] The first mass-produced CMOS consumer electronic product was the Hamilton Pulsar "Wrist Computer" digital watch, released in 1970. [19] Due to low power consumption, CMOS logic has been widely used for calculators and watches since the 1970s. [6]

The earliest microprocessors in the early 1970s were PMOS processors, which initially dominated the early microprocessor industry. By the late 1970s, NMOS microprocessors had overtaken PMOS processors. [20] CMOS microprocessors were introduced in 1975, with the Intersil 6100, [20] MOS Technology 6502 [21] and RCA CDP 1801. [22] However, CMOS processors did not become dominant until the 1980s. [20]

CMOS was initially slower than NMOS logic, thus NMOS was more widely used for computers in the 1970s. [6] The Intel 5101 (1  kb SRAM) CMOS memory chip (1974) had an access time of 800  ns, [23] [24] whereas the fastest NMOS chip at the time, the Intel 2147 (4 kb SRAM) HMOS memory chip (1976), had an access time of 55/70 ns. [6] [24] In 1978, a Hitachi research team led by Toshiaki Masuhara introduced the twin-well Hi-CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a 3 μm process. [6] [25] [26] The Hitachi HM6147 chip was able to match the performance (55/70 ns access) of the Intel 2147 HMOS chip, while the HM6147 also consumed significantly less power (15  mA) than the 2147 (110 mA). With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computers in the 1980s. [6]

In the 1980s, CMOS microprocessors overtook NMOS microprocessors. [20] NASA's Galileo spacecraft, sent to orbit Jupiter in 1989, used the RCA 1802 CMOS microprocessor due to low power consumption. [19]

Intel introduced a 1.5 μm process for CMOS semiconductor device fabrication in 1983. [27] In the mid-1980s, Bijan Davari of IBM developed high-performance, low-voltage, deep sub-micron CMOS technology, which enabled the development of faster computers as well as portable computers and battery-powered handheld electronics. [28] In 1988, Davari led an IBM team that demonstrated a high-performance 250 nanometer CMOS process. [29]

Fujitsu commercialized a 700  nm CMOS process in 1987, [27] and then Hitachi, Mitsubishi Electric, NEC and Toshiba commercialized 500 nm CMOS in 1989. [30] In 1993, Sony commercialized a 350 nm CMOS process, while Hitachi and NEC commercialized 250 nm CMOS. Hitachi introduced a 160 nm CMOS process in 1995, then Mitsubishi introduced 150 nm CMOS in 1996, and then Samsung Electronics introduced 140 nm in 1999. [30]

In 2000, Gurtej Singh Sandhu and Trung T. Doan at Micron Technology invented atomic layer deposition High-κ dielectric films, leading to the development of a cost-effective 90 nm CMOS process. [28] [31] Toshiba and Sony developed a 65 nm CMOS process in 2002, [32] and then TSMC initiated the development of 45 nm CMOS logic in 2004. [33] The development of pitch double patterning by Gurtej Singh Sandhu at Micron Technology led to the development of 30 nm class CMOS in the 2000s. [28]

CMOS is used in most modern LSI and VLSI devices. [6] As of 2010, CPUs with the best performance per watt each year have been CMOS static logic since 1976.[ citation needed ] As of 2019, planar CMOS technology is still the most common form of semiconductor device fabrication, but is gradually being replaced by non-planar FinFET technology, which is capable of manufacturing semiconductor nodes smaller than 20 nm. [34]

## Inversion

CMOS circuits are constructed in such a way that all P-type metal–oxide–semiconductor (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output, therefore, registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

### Power supply pins

The power supply pins for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies. [35] These do not apply directly to CMOS, since both supplies are really source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

### Duality

An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

### Logic

More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.

### Example: NAND gate in physical layout

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the NAND (illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup.

## Power: switching and leakage

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from Vdd to Vss through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

### Static dissipation

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current (called sub threshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of the transistor used in some CMOS circuits is the native transistor, with near zero threshold voltage.

SiO2 is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily.

### Dynamic dissipation

#### Charging and discharging of load capacitances

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=CLVDD is thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: ${\displaystyle P=0.5CV^{2}f}$.

Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor ${\displaystyle \alpha }$, called the activity factor. Now, the dynamic power dissipation may be re-written as ${\displaystyle P=\alpha CV^{2}f}$.

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1. [36] If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD to ground, hence creating a short-circuit current. Short-circuit power dissipation increases with rise and fall time of the transistors.

An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from VDD to VSS. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS power.

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a Vth of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Multi-threshold CMOS (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high Vth transistors are used when switching speed is not critical, while low Vth transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional leakage component because of current tunnelling through the extremely thin gate dielectric. Using high-κ dielectrics instead of silicon dioxide that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS. [37]

## Input protection

Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g. electrostatic discharges or line reflections. The resulting latch-up may damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.

## Analog CMOS

Besides digital applications, CMOS technology is also used in analog applications. For example, there are CMOS operational amplifier ICs available in the market. Transmission gates may be used as analog multiplexers instead of signal relays. CMOS technology is also widely used for RF circuits all the way to microwave frequencies, in mixed-signal (analog+digital) applications.[ citation needed ]

### RF CMOS

RF CMOS refers to RF circuits (radio frequency circuits) which are based on mixed-signal CMOS integrated circuit technology. They are widely used in wireless telecommunication technology. RF CMOS was developed by Asad Abidi while working at UCLA in the late 1980s. This changed the way in which RF circuits were designed, leading to the replacement of discrete bipolar transistors with CMOS integrated circuits in radio transceivers. [38] It enabled sophisticated, low-cost and portable end-user terminals, and gave rise to small, low-cost, low-power and portable units for a wide range of wireless communication systems. This enabled "anytime, anywhere" communication and helped bring about the wireless revolution, leading to the rapid growth of the wireless industry. [39]

The baseband processors [40] [41] and radio transceivers in all modern wireless networking devices and mobile phones are mass-produced using RF CMOS devices. [38] RF CMOS circuits are widely used to transmit and receive wireless signals, in a variety of applications, such as satellite technology (such as GPS), bluetooth, Wi-Fi, near-field communication (NFC), mobile networks (such as 3G and 4G), terrestrial broadcast, and automotive radar applications, among other uses. [42]

Examples of commercial RF CMOS chips include Intel's DECT cordless phone, and 802.11 (Wi-Fi) chips created by Atheros and other companies. [43] Commercial RF CMOS products are also used for Bluetooth and Wireless LAN (WLAN) networks. [44] RF CMOS is also used in the radio transceivers for wireless standards such as GSM, Wi-Fi, and Bluetooth, transceivers for mobile networks such as 3G, and remote units in wireless sensor networks (WSN). [45]

RF CMOS technology is crucial to modern wireless communications, including wireless networks and mobile communication devices. One of the companies that commercialized RF CMOS technology was Infineon. Its bulk CMOS RF switches sell over 1 billion units annually, reaching a cumulative 5 billion units, as of 2018. [46]

## Temperature range

Conventional CMOS devices work over a range of –55 °C to +125 °C.

There were theoretical indications as early as August 2008 that silicon CMOS will work down to –233 °C (40  K). [47] Functioning temperatures near 40 K have since been achieved using overclocked AMD Phenom II processors with a combination of liquid nitrogen and liquid helium cooling. [48]

## Single-electron MOS transistors

Ultra small (L = 20 nm, W = 20 nm) MOSFETs achieve the single-electron limit when operated at cryogenic temperature over a range of –269 °C (4  K) to about –258 °C (15  K). The transistor displays Coulomb blockade due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many. [49]

## Related Research Articles

A logic gate is an idealized or physical electronic device implementing a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.

A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of insulated-gate field-effect transistor (IGFET) that is fabricated by the controlled oxidation of a semiconductor, typically silicon. The voltage of the covered gate determines the electrical conductivity of the device; this ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in November 1959. It is the basic building block of modern electronics, and the most frequently manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.

N-type metal-oxide-semiconductor logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off, triode, saturation, and velocity saturation.

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right.

Bipolar CMOS (BiCMOS) is a semiconductor technology that integrates two formerly separate semiconductor technologies, those of the bipolar junction transistor and the CMOS gate, in a single integrated circuit device.

In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family. Many logic families were produced as individual components, each containing one or a few related basic logical functions, which could be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated circuits. A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption and delay.

A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier nMOS logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

Power optimization is the use of electronic design automation tools to optimize (reduce) the power consumption of a digital design, such as that of an integrated circuit, while preserving the functionality.

An active-pixel sensor (APS) is an image sensor where each pixel sensor unit cell has a photodetector and one or more active transistors. In a metal–oxide–semiconductor (MOS) active-pixel sensor, MOS field-effect transistors (MOSFETs) are used as amplifiers. There are different types of APS, including the early NMOS APS and the much more common complementary MOS (CMOS) APS, also known as the CMOS sensor, which is widely used in digital camera technologies such as cell phone cameras, web cameras, most modern digital pocket cameras, most digital single-lens reflex cameras (DSLRs), and mirrorless interchangeable-lens cameras (MILCs). CMOS sensors emerged as an alternative to charge-coupled device (CCD) image sensors and eventually outsold them by the mid-2000s.

The floating-gate MOSFET (FGMOS), also known as a floating-gate transistor, is a type of MOSFET where the gate is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify the amount of charge stored in the FG.

Four-phase logic is a type of, and design methodology for dynamic logic. It enabled non-specialist engineers to design quite complex ICs, using either PMOS or NMOS processes. It uses a kind of 4-phase clock signal.

P-type metal-oxide-semiconductor logic uses p-channel (+) metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-type transistor body. This inversion layer, called the p-channel, can conduct holes between p-type "source" and "drain" terminals.

A transistor is a semiconductor device with at least three terminals for connection to an electric circuit. The vacuum-tube triode, also called a (thermionic) valve, was the transistor's precursor, introduced in 1907. The principle of a field-effect transistor was proposed by Julius Edgar Lilienfeld in 1925.

In field effect transistors (FETs), depletion mode and enhancement mode are two major transistor types, corresponding to whether the transistor is in an ON state or an OFF state at zero gate–source voltage.

A FET amplifier is an amplifier that uses one or more field-effect transistors (FETs). The most common type of FET amplifier is the MOSFET amplifier, which uses metal–oxide–semiconductor FETs (MOSFETs). The main advantage of a FET used for amplification is that it has very high input impedance and low output impedance.

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 and reset to store a logic 0. Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

## References

1. "What is CMOS Memory?". Wicked Sago. Archived from the original on 26 September 2014. Retrieved 3 March 2013.
2. Voinigescu, Sorin (2013). High-Frequency Integrated Circuits. Cambridge University Press. p. 164. ISBN   9780521873024.
3. Fairchild. Application Note 77. "CMOS, the Ideal Logic Family" Archived 2015-01-09 at the Wayback Machine . 1983.
4. "Intel® Architecture Leads the Microarchitecture Innovation Field". Intel. Archived from the original on 29 June 2011. Retrieved 2 May 2018.
5. Baker, R. Jacob (2008). CMOS: circuit design, layout, and simulation (Second ed.). Wiley-IEEE. p. xxix. ISBN   978-0-470-22941-5.
6. "1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor History Museum of Japan. Retrieved 5 July 2019.
7. Higgins, Richard J. (1983). . Prentice-Hall. p.  101. ISBN   9780132507042. The dominant difference is power: CMOS gates can consume about 100,000 times less power than their TTL equivalents!
8. Stephens, Carlene; Dennis, Maggie (2000). "Engineering Time: Inventing the Electronic Wristwatch" (PDF). The British Journal for the History of Science . Cambridge University Press. 33 (4): 477–497 (485). ISSN   0007-0874.
9. "1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine: A Timeline of Semiconductors in Computers. Computer History Museum . Retrieved August 31, 2019.
10. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. pp. 321–3. ISBN   9783540342588.
11. Sah, Chih-Tang (October 1988). "Evolution of the MOS transistor-from conception to VLSI" (PDF). Proceedings of the IEEE . 76 (10): 1280–1326 (1290). doi:10.1109/5.16328. ISSN   0018-9219. Those of us active in silicon material and device research during 1956–1960 considered this successful effort by the Bell Labs group led by Atalla to stabilize the silicon surface the most important and significant technology advance, which blazed the trail that led to silicon integrated circuit technology developments in the second phase and volume production in the third phase.
12. "1963: Complementary MOS Circuit Configuration is Invented". Computer History Museum . Retrieved 6 July 2019.
13. Sah, Chih-Tang; Wanlass, Frank (1963). "Nanowatt logic using field-effect metal-oxide semiconductor triodes". 1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. VI: 32–33. doi:10.1109/ISSCC.1963.1157450.
14. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. p. 330. ISBN   9783540342588.
15. Gilder, George (1990). . Simon and Schuster. pp.  144–5. ISBN   9780671705923.
16. "1972 to 1973: CMOS LSI circuits for calculators (Sharp and Toshiba)" (PDF). Semiconductor History Museum of Japan. Retrieved 5 July 2019.
17. "Early 1970s: Evolution of CMOS LSI circuits for watches" (PDF). Semiconductor History Museum of Japan. Retrieved 6 July 2019.
18. "Tortoise of Transistors Wins the Race - CHM Revolution". Computer History Museum . Retrieved 22 July 2019.
19. Kuhn, Kelin (2018). "CMOS and Beyond CMOS: Scaling Challenges". High Mobility Materials for CMOS Applications. Woodhead Publishing. p. 1. ISBN   9780081020623.
20. Cushman, Robert H. (20 September 1975). "2-1/2-generation μP's-\$10 parts that perform like low-end mini's" (PDF). EDN.
21. "CDP 1800 μP Commercially available" (PDF). Microcomputer Digest. 2 (4): 1–3. October 1975.
22. "Silicon Gate MOS 2102A". Intel . Retrieved 27 June 2019.
23. "A chronological list of Intel products. The products are sorted by date" (PDF). Intel museum. Intel Corporation. July 2005. Archived from the original (PDF) on August 9, 2007. Retrieved July 31, 2007.
24. Masuhara, Toshiaki; Minato, Osamu; Sasaki, Toshio; Sakai, Yoshio; Kubo, Masaharu; Yasui, Tokumasa (February 1978). "A high-speed, low-power Hi-CMOS 4K static RAM". 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXI: 110–111. doi:10.1109/ISSCC.1978.1155749.
25. Masuhara, Toshiaki; Minato, Osamu; Sakai, Yoshi; Sasaki, Toshio; Kubo, Masaharu; Yasui, Tokumasa (September 1978). "Short Channel Hi-CMOS Device and Circuits". ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers: 131–132.
26. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). CORE . Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019.
27. "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers . Retrieved 4 July 2019.
28. Davari, Bijan; et al. (1988). "A high-performance 0.25 micrometer CMOS technology". International Electron Devices Meeting.
29. "Memory". STOL (Semiconductor Technology Online). Retrieved 25 June 2019.
30. Sandhu, Gurtej; Doan, Trung T. (22 August 2001). "Atomic layer doping apparatus and method". Google Patents . Retrieved 5 July 2019.
31. "Toshiba and Sony Make Major Advances in Semiconductor Process Technologies". Toshiba . 3 December 2002. Retrieved 26 June 2019.
32. "A Banner Year: TSMC Annual Report 2004" (PDF). TSMC . Retrieved 5 July 2019.
33. "Global FinFET Technology Market 2024 Growth Analysis by Manufacturers, Regions, Type and Application, Forecast Analysis". Financial Planning. July 3, 2019. Retrieved 6 July 2019.
34. "Archived copy" (PDF). Archived from the original (PDF) on 2011-12-09. Retrieved 2011-11-25.CS1 maint: archived copy as title (link)
35. K. Moiseev, A. Kolodny and S. Wimer, "Timing-aware power-optimal ordering of signals", ACM Transactions on Design Automation of Electronic Systems, Volume 13 Issue 4, September 2008, ACM
36. A good overview of leakage and reduction methods are explained in the book Leakage in Nanometer CMOS Technologies Archived 2011-12-02 at the Wayback Machine ISBN   0-387-25737-3.
37. O'Neill, A. (2008). "Asad Abidi Recognized for Work in RF-CMOS". IEEE Solid-State Circuits Society Newsletter. 13 (1): 57–58. doi:10.1109/N-SSC.2008.4785694. ISSN   1098-4232.
38. Daneshrad, Babal; Eltawil, Ahmed M. (2002). "Integrated Circuit Technologies for Wireless Communications". Wireless Multimedia Network Technologies. Springer US: 227–244. doi:10.1007/0-306-47330-5_13.
39. Chen, Wai-Kai (2018). The VLSI Handbook. CRC Press. pp. 60–2. ISBN   9781420005967.
40. Morgado, Alonso; Río, Rocío del; Rosa, José M. de la (2011). Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio. Springer Science & Business Media. p. 1. ISBN   9781461400370.
41. Veendrick, Harry J. M. (2017). Nanometer CMOS ICs: From Basics to ASICs. Springer. p. 243. ISBN   9783319475974.
42. Nathawad, L.; Zargari, M.; Samavati, H.; Mehta, S.; Kheirkhaki, A.; Chen, P.; Gong, K.; Vakili-Amini, B.; Hwang, J.; Chen, M.; Terrovitis, M.; Kaczynski, B.; Limotyrakis, S.; Mack, M.; Gan, H.; Lee, M.; Abdollahi-Alibeik, B.; Baytekin, B.; Onodera, K.; Mendis, S.; Chang, A.; Jen, S.; Su, D.; Wooley, B. "20.2: A Dual-band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN" (PDF). IEEE Entity Web Hosting. IEEE. Retrieved 22 October 2016.
43. "Abidi Receives IEEE Pederson Award at ISSCC 2008" (PDF). SSCC: IEEE Solid-State Circuits Society News . 13 (2): 12. Spring 2008.
44. Oliveira, Joao; Goes, João (2012). Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies. Springer Science & Business Media. p. 7. ISBN   9781461416708.
45. "Infineon Hits Bulk-CMOS RF Switch Milestone". EE Times . 20 November 2018. Retrieved 26 October 2019.
46. Edwards C, "Temperature control", Engineering & Technology 26 July  8 August 2008, IET
47. Moorhead, Patrick (January 15, 2009). "Breaking Records with Dragons and Helium in the Las Vegas Desert". blogs.amd.com/patmoorhead. Archived from the original on September 15, 2010. Retrieved 2009-09-18.
48. Prati, E.; De Michielis, M.; Belli, M.; Cocco, S.; Fanciulli, M.; Kotekar-Patil, D.; Ruoff, M.; Kern, D. P.; Wharam, D. A.; Verduijn, J.; Tettamanzi, G. C.; Rogge, S.; Roche, B.; Wacquez, R.; Jehl, X.; Vinet, M.; Sanquer, M. (2012). "Few electron limit of n-type metal oxide semiconductor single electron transistors" (PDF). Nanotechnology. 23 (21): 215204. arXiv:. Bibcode:2012Nanot..23u5204P. doi:10.1088/0957-4484/23/21/215204. PMID   22552118. Archived (PDF) from the original on 2014-10-04.