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In computing, Direct Media Interface (DMI) is Intel's proprietary link between the northbridge and southbridge on a computer motherboard. It was first used between the 9xx chipsets and the ICH6, released in 2004. Previous Intel chipsets had used the Intel Hub Architecture to perform the same function, and server chipsets use a similar interface called Enterprise Southbridge Interface (ESI). –southbridge combination is allowed.While the "DMI" name dates back to ICH6, Intel mandates specific combinations of compatible devices, so the presence of a DMI interface does not guarantee by itself that a particular northbridge
DMI shares many characteristics with PCI Express, using multiple lanes and differential signaling to form a point-to-point link. Most implementations use a ×4 link, while some mobile systems (e.g. 915GMS, 945GMS/GSE/GU and the Atom N450) use a ×2 link, halving the bandwidth. The original implementation provides 10 Gbit/s (1 GB/s) in each direction using a ×4 link.
DMI 2.0, introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link. It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge. :14
DMI 3.0, released in August 2015, allows the 8 GT/s transfer rate per lane, for a total of four lanes and 3.93 GB/s for the CPU–PCH link. It is used by two-chip variants of the Intel Skylake microprocessors, which are used in conjunction with Intel 100 Series chipsets; some low power (Skylake-U onwards) and ultra low power (Skylake-Y onwards) mobile Intel processors have the PCH integrated into the physical package as a separate die, referred to as OPI (On Package DMI interconnect Interface) and effectively following the system on a chip (SoC) design layout. On 9 March 2015, Intel announced the Broadwell-based Xeon D as its first enterprise platform to fully incorporate the PCH in an SoC configuration.
In 2021, with the release of 500 series chipsets, Intel increased the amount of DMI 3.0 lanes from four to eight, doubling the bandwidth.
DMI 4.0, set for release in 2021 with 600 series chipsets, will have 8 lanes each providing 16 GT/s, two times faster compared to DMI 3.0 x8.
Northbridge devices supporting a northbridge DMI are the Intel 915-series, 925-series, 945-series, 955-series, 965-series, 975-series, G31/33, P35, X38, X48, P45 and X58 [ citation needed ].
Processors supporting a northbridge DMI and, therefore, not using a separate northbridge, are the Intel Atom, Intel Core i3, Intel Core i5, and Intel Core i7 (8xx, 7xx and 6xx, but not 9xx). Processors supporting a northbridge DMI 2.0 and, therefore not using a separate northbridge, are the 2000, 3000, 4000, and 5000 series of the Intel Core i3, Core i5 and Core i7.
Southbridge devices supporting a southbridge DMI are the ICH6, ICH7, ICH8, ICH9, ICH10, NM10, P55, H55, H57, Q57, PM55, HM55, HM57, QM57 and QS57[ citation needed ].
PCH devices supporting DMI 2.0 are the Intel B65, H61, H67, P67, Q65, Q67, Z68, HM65, HM67, QM67, QS67, B75, H77, Q75, Q77, Z75, Z77, X79, HM75, HM76, HM77, QM77, QS77, UM77, H81, B85, Q85, Q87, H87, Z87, H97, Z97, C222, C224, C226, X99, H110, and H310.
PCH devices supporting DMI 3.0 are the Intel Z170, H170, HM170, Q170, QM170, Q150, B150, C236, CM236, C232, and C620. The Intel 200 series, B360, H370, Q370, Z370, Z390, C246, and Intel 400 series chipsets also support DMI 3.0.
In a computer system, a chipset is a set of electronic components in an integrated circuit known as a "Data Flow Management System" that manages the data flow between the processor, memory and peripherals. It is usually found on the motherboard. Chipsets are usually designed to work with a specific family of microprocessors. Because it controls communications between the processor and external devices, the chipset plays a crucial role in determining system performance.
The southbridge is one of the two chips in the core logic chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In systems with Intel chipsets, the southbridge is named I/O Controller Hub (ICH), while AMD has named its southbridge Fusion Controller Hub (FCH) since the introduction of its Fusion AMD Accelerated Processing Unit (APU) while moving the functions of the Northbridge onto the CPU die, hence making it similar in function to the Platform hub controller.
I/O Controller Hub (ICH) is a family of Intel southbridge microchips used to manage data communications between a CPU and a motherboard, specifically Intel chipsets based on the Intel Hub Architecture. It is designed to be paired with a second support chip known as a northbridge. As with any other southbridge, the ICH is used to connect and control peripheral devices.
PCI IDE ISA Xcelerator (PIIX), also known as Intel 82371, is a family of Intel southbridge microchips employed in some Intel chipsets. x86 virtualization implementations often support emulations of various PIIX-based chipsets.
The Intel X58 is an Intel chip designed to connect Intel processors with Intel QuickPath Interconnect (QPI) interface to peripheral devices. Supported processors implement the Nehalem microarchitecture and therefore have an integrated memory controller (IMC), so the X58 does not have a memory interface. Initially supported processors were the Core i7, but the chip also supported Nehalem and Westmere-based Xeon processors.
The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips - a northbridge and southbridge instead, and first appeared in the Intel 5 Series.
LGA 1366, also known as Socket B, is an Intel CPU socket. This socket supersedes Intel's LGA 775 in the high-end and performance desktop segments. It also replaces the server-oriented LGA 771 in the entry level and is superseded itself by LGA 2011. This socket has 1,366 protruding pins which touch contact points on the underside of the processor (CPU) and accesses up to three channels of DDR3 memory via the processor's internal memory controller.
LGA 1156, also known as Socket H or H1, is an Intel desktop CPU socket. Its incompatible successor is LGA 1155.
Intel 5 Series is a computing architecture introduced in 2008 that improves the efficiency and balances the use of communication channels in the motherboard. The architecture consists primarily of a central processing unit (CPU) and a single chipset. All motherboard communications and activities circle around these two devices.
FDI or Flexible Display Interface is an interconnect created by Intel in order to allow the communication of the HD Graphics integrated GPU found on supported CPUs with the PCH southbridge where display connectors are attached. It provides a path between an Intel processor and an Intel southbridge on a computer motherboard which carries display data from the graphics controller of the Intel processor package to the display connectors attached at some PCH versions. It is based on DisplayPort standard. Currently it supports 2 independent 4-bit fixed frequency links/channels/pipes at 2.7Gbit/s data rate. It was first used with the 2010 Core i3, i5 processors and H55, H57, Q57, 3450 southbridges released in 2010. FDI enabled processors require FDI enabled southbridge in order to utilize the graphics controller capability, thus boards based on P55, PM55, and P67 will not be able to take advantage of the graphics controller present on later processors. An FDI capable southbridge and CPU pair is not usable without the existence of the appropriate video connectors on the mainboard.
LGA 2011, also called Socket R, is a CPU socket by Intel. Released on November 14, 2011, it replaces Intel's LGA 1366 and LGA 1567 in the performance and high-end desktop and server platforms. The socket has 2011 protruding pins that touch contact points on the underside of the processor.
GPU switching is a mechanism used on computers with multiple graphic controllers. This mechanism allows the user to either maximize the graphic performance or prolong battery life by switching between the graphic cards. It is mostly used on gaming laptops which usually have an integrated graphic device and a discrete video card.
LGA 1155, also called Socket H2, is a socket used for Intel microprocessors based on Sandy Bridge and Ivy Bridge microarchitectures.
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a "tock" in Intel's "tick–tock" manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Cannon Lake, Whiskey Lake, and Comet Lake CPUs.
LGA 1150, also known as Socket H3, is a microprocessor socket used by Intel's central processing units (CPUs) built on the Haswell microarchitecture. This socket is also used by the Haswell's successor, Broadwell microarchitecture.
Broadwell is the fifth generation of the Intel Core Processor. It's Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell.
LGA 1151, also known as Socket H4, is an Intel microprocessor compatible socket which comes in two distinct versions: the first revision which supports both Intel's Skylake and Kaby Lake CPUs, and the second revision which supports Coffee Lake CPUs exclusively.
Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's previous "tick–tock" manufacturing and design model, Kaby Lake represents the optimized step of the newer process–architecture–optimization model. Kaby Lake began shipping to manufacturers and OEMs in the second quarter of 2016, and mobile chips have started shipping while Kaby Lake (desktop) chips were officially launched in January 2017.