Embedded Wafer Level Ball Grid Array

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Embedded Wafer Level Ball Grid Array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.

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Principle eWLB EWLB Sketch e.png
Principle eWLB

eWLB is a further development of the classical Wafer Level Ball Grid Array Technology (WLB or WLP: wafer level package). The main driving force behind the eWLB technology was to allow fanout and more space for interconnect routing.

All process steps for the generation of the package are performed on the wafer. This allows, in comparison to classical packaging technologies (e. g. ball grid array), the generation of very small and flat packages with excellent electrical and thermal performance at lowest cost. It is common for all WLB technologies, which are built on a silicon wafer, that the interconnects (typically solder balls) fit on the chip (so called fan-in design). Therefore only chips with a restricted number of interconnects can be packaged.

Ball grid array

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

Solder ball

In integrated circuit packaging, a solder ball, also a solder bump is a ball of solder that provides the contact between the chip package and the printed circuit board, as well as between stacked packages in multichip modules; in the latter case, they may be referred to as microbumps, since they are usually significantly smaller than the former. The solder balls can be placed manually or by automated equipment, and are held in place with a tacky flux.

Cross Section eWLB EWLB Crossection e.png
Cross Section eWLB

The eWLB technology allows the realization of chips with a high number of interconnects. The package is not created on a silicon wafer as for the classical Wafer Level Package, but on an artificial wafer. Therefore a front-end-processed wafer is diced and the singulated chips are placed on a carrier. The distance between the chips can be chosen freely, but it is typically larger than on the silicon wafer. The gaps and the edges around the chips are now filled with a casting compound to form a wafer. After curing an artificial wafer containing a mold frame around the dies for carrying additional interconnect elements is created. After the build of the artificial wafer (the so-called Reconstitution) the electrical connections from the chip pads to the interconnects are made in thin-film technology, as for any other classical Wafer Level Package.

With this technology any number of additional interconnects can be realized on the package in an arbitrary distance (fan-out design). Therefore, this Wafer Level Packaging Technology can also be used for space sensitive applications, where the chip area wouldn’t be sufficient to place the required number of interconnects at a suitable distance. The eWLB Technology was developed by Infineon, STMicroelectronics and STATS ChipPAC Ltd. [1] First components were brought into market mid of 2009 (mobile phone).

Infineon Technologies company

Infineon Technologies AG is a German semiconductor manufacturer founded on 1 April 1999, when the semiconductor operations of the parent company Siemens AG were spun off to form a separate legal entity. As of 30 September 2018, Infineon had 40,100 employees worldwide. In fiscal year 2018, the company achieved sales of €7.599 billion.

STMicroelectronics French-Italian multinational electronics and semiconductor manufacturer headquartered in Schiphol, Amsterdam (Netherlands)

STMicroelectronics is a French-Italian multinational electronics and semiconductor manufacturer headquartered in Geneva, Switzerland. It is commonly called ST, and it is Europe's largest semiconductor chip maker based on revenue. While STMicroelectronics corporate headquarters and the headquarters for EMEA region are based in Geneva, the holding company, STMicroelectronics N.V. is registered in Amsterdam, Netherlands.

Process Steps

  1. Lamination of foil onto carrier (Lamination tool)
  2. Chip placement onto wafer (Pick and place tool)
  3. Molding (Mold press)
  4. De-Bonding of carrier (de-bonding tool)
  5. Flip reconstructed wafer
  6. Ball drop reflow and wafer test

Advantages

Disadvantages

See also

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