FinFET

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A double-gate FinFET device Doublegate FinFET.PNG
A double-gate FinFET device

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal-oxide-semiconductor) technology.

Multigate device type of MOS field-effect transistor with more than one gate

A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a MOSFET that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are the FinFET and the GAAFET, which are non-planar transistors, or 3D transistors.

MOSFET Transistor used for amplifying or switching electronic signals.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of field-effect transistor that is fabricated by the controlled oxidation of a semiconductor, typically silicon. It has a covered gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in November 1959. It is the basic building block of modern electronics, and the most widely manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.

Field-effect transistor transistor that uses an electric field to control the electrical behaviour of the device. FETs are also known as unipolar transistors since they involve single-carrier-type operation

The field-effect transistor (FET) is an electronic device which uses an electric field to control the flow of current. FETs are devices with three terminals: source, gate, and drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source.

Contents

FinFET is a type of non-planar transistor, or "3D" transistor. [1] It is the basis for modern nanoelectronic semiconductor device fabrication. Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm, 10 nm and 7 nm process nodes.

Semiconductor device fabrication manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

History

20 years after the MOSFET was first demonstrated by Mohamed Atalla and Dawon Kahng of Bell Labs in 1960, [2] the concept of a double-gate MOSFET was proposed by Toshihiro Sekigawa of the Electrotechnical Laboratory (ETL) in a 1980 patent describing the planar XMOS transistor. [3] Sekigawa fabricated the XMOS transistor with Yutaka Hayashi at the ETL in 1984. They demonstrated that short-channel effects can be significantly reduced by sandwiching a fully depleted silicon-on-insulator (SOI) device between two gate electrodes connected together. [4] [5]

Dawon Kahng South Korean engineer

Dawon Kahng was a Korean-American electrical engineer and inventor, known for his work in solid-state electronics. He is best known for inventing the MOSFET, also known as the MOS transistor, with Mohamed Atalla in 1959. Atalla and Kahng developed both the PMOS and NMOS processes for MOSFET semiconductor device fabrication. The MOSFET is the most widely used type of transistor, and the basic element in most modern electronic equipment.

Bell Labs Research and scientific development company

Nokia Bell Labs is an industrial research and scientific development company owned by Finnish company Nokia. With headquarters located in Murray Hill, New Jersey, the company operates several laboratories in the United States and around the world. Bell Labs has its origins in the complex past of the Bell System.

Patent Intellectual property conferring a monopoly on a new invention

A patent is a form of intellectual property that gives its owner the legal right to exclude others from making, using, selling, and importing an invention for a limited period of years, in exchange for publishing an enabling public disclosure of the invention. In most countries patent rights fall under civil law and the patent holder needs to sue someone infringing the patent in order to enforce his or her rights. In some industries patents are an essential form of competitive advantage; in others they are irrelevant.

The first finfet transistor type was called a "Depleted Lean-channel Transistor" or "DELTA" transistor, which was first fabricated in Japan by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. [4] [6] [7] The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called split transistor. This enables more refined control of the operation of the transistor.

Hitachi Japanese multinational engineering and electronics company

Hitachi, Ltd. is a Japanese multinational conglomerate company headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group and forms part of the DKB Group of companies. Hitachi is a highly diversified company that operates eleven business segments: Information & Telecommunication Systems, Social Infrastructure, High Functional Materials & Components, Financial Services, Power Systems, Electronic Systems & Equipment, Automotive Systems, Railway & Urban Systems, Digital Media & Consumer Products, Construction Machinery and Other Components & Systems.

Indonesian engineer Effendi Leobandung, while working at the University of Minnesota, published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width. [8] This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins. [9] The device had a 35 nm channel width and 70 nm channel length. [8]

University of Minnesota public research university in Minneapolis and Saint Paul, Minnesota, United States

The University of Minnesota is a public research university in Minneapolis and Saint Paul, Minnesota. The Minneapolis and St. Paul campuses are approximately 3 miles (4.8 km) apart, and the St. Paul campus is actually in neighboring Falcon Heights. It is the oldest and largest campus within the University of Minnesota system and has the sixth-largest main campus student body in the United States, with 50,943 students in 2018-19. It is the flagship institution of the University of Minnesota System, and is organized into 19 colleges and schools, with sister campuses in Crookston, Duluth, Morris, and Rochester.

CMOS Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuits (ICs), including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

Transistor Basic electronics component

A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits.

The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at UC Berkeley to develop a deep sub-micron transistor based on DELTA technology. [10] The group was led by Hisamoto along with TSMC's Chenming Hu. The team made the following breakthroughs between 1998 and 2004. [11]

DARPA Agency of the U.S. Department of Defense responsible for the development of new technologies

The Defense Advanced Research Projects Agency (DARPA) is an agency of the United States Department of Defense responsible for the development of emerging technologies for use by the military.

University of California, Berkeley Public university in California, USA

The University of California, Berkeley is a public research university in Berkeley, California. It was founded in 1868 and serves as the flagship campus of the ten campuses of the University of California. Berkeley has since grown to instruct over 40,000 students in approximately 350 undergraduate and graduate degree programs covering numerous disciplines.

Nanoelectronics refers to the use of nanotechnology in electronic components. The term covers a diverse set of devices and materials, with the common characteristic that they are so small that inter-atomic interactions and quantum mechanical properties need to be studied extensively. Some of these candidates include: hybrid molecular/semiconductor electronics, one-dimensional nanotubes/nanowires or advanced molecular electronics.

They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper, [16] used to describe a non-planar, double-gate transistor built on an SOI substrate. [17]

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology. [18] [19] In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates. [20]

Commercialization

The industry's first 25 nanometer transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004, Samsung demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory (DRAM) manufactured with a 90 nm Bulk FinFET process. [11]

In 2011, Intel demonstrated tri-gate transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors. [21] [22] [23]

Commercially produced chips at 22 nm and below have utilised FinFET gate designs. Intel's "Tri-Gate" variant were announced at 22nm in 2011 for its Ivy Bridge microarchitecture. [24] These devices shipped from 2012 onwards. From 2014 onwards, at 14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries) utilised FinFET designs.

In 2013, SK Hynix began commercial mass-production of a 16 nm process, [25] TSMC began production of a 16 nm FinFET process, [26] and Samsung Electronics began production of a 10 nm process. [27] TSMC began production of a 7 nm process in 2017, [28] and Samsung began production of a 5 nm process in 2018. [29] In 2019, Samsung announced plans for the commercial production of a 3 nm GAAFET process by 2021. [30]

Commercial production of nanoelectronic FinFET semiconductor memory began in the 2010s. In 2013, SK Hynix began mass-production of 16 nm NAND flash memory, [25] and Samsung Electronics began production of 10 nm multi-level cell (MLC) NAND flash memory. [27] In 2017, TSMC began production of SRAM memory using a 7 nm process. [28]

See also

Reference

  1. "What is Finfet?". Computer Hope . April 26, 2017. Retrieved 4 July 2019.
  2. "1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum . Retrieved 25 September 2019.
  3. Koike, Hanpei; Nakagawa, Tadashi; Sekigawa, Toshiro; Suzuki, E.; Tsutsumi, Toshiyuki (23 February 2003). "Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode" (PDF). TechConnect Briefs. 2 (2003): 330–333.
  4. 1 2 Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. pp. 11 & 39. ISBN   9780387717517.
  5. Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. doi:10.1016/0038-1101(84)90036-4. ISSN   0038-1101.
  6. Hisamoto, Digh; Kaga, Toru; Kawamoto, Yoshifumi; Takeda, Eiji (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting: 833–836. doi:10.1109/IEDM.1989.74182.
  7. "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award . Institute of Electrical and Electronics Engineers . Retrieved 4 July 2019.
  8. 1 2 Leobandung, Effendi; Chou, Stephen Y. (1996). "Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length". 1996 54th Annual Device Research Conference Digest: 110–111. doi:10.1109/DRC.1996.546334.
  9. Leobandung, Effendi (June 1996). Nanoscale MOSFETs and single charge transistors on SOI. Minneapolis, MN: U of Minnesota, Ph.D. Thesis. p. 72.
  10. "The Breakthrough Advantage for FPGAs with Tri-Gate Technology" (PDF). Intel. 2014. Retrieved 4 July 2019.
  11. 1 2 Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley . Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019.
  12. Hisamoto, Digh; Hu, Chenming; Liu, Tsu-Jae King; Bokor, Jeffrey; Lee, Wen-Chin; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki; Asano, Kazuya (December 1998). "A folded-channel MOSFET for deep-sub-tenth micron era". International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217): 1032–1034. doi:10.1109/IEDM.1998.746531.
  13. Hisamoto, Digh; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki (December 1999). "Sub 50-nm FinFET: PMOS" (PDF). International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318): 67–70. doi:10.1109/IEDM.1999.823848.
  14. Hu, Chenming; Choi, Yang‐Kyu; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; Bokor, J.; Tsu-Jae King, Liu (December 2001). "Sub-20 nm CMOS FinFET technologies". International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224): 19.1.1–19.1.4. doi:10.1109/IEDM.2001.979526.
  15. Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting : 251–254. doi:10.1109/IEDM.2002.1175825.
  16. Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX   10.1.1.211.204 . doi:10.1109/16.887014.
  17. Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, Charles; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. Bibcode:2001ITED...48..880H. doi:10.1109/16.918235.
  18. "Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
  19. Lee, Hyunjin; et al. (2006), "Sub-5nm All-Around Gate FinFET for Ultimate Scaling", Symposium on VLSI Technology, 2006: 58–59, doi:10.1109/VLSIT.2006.1705215, hdl:10203/698, ISBN   978-1-4244-0005-8
  20. Rostami, M.; Mohanram, K. (2011). "IEEE Xplore Abstract - Dual- Independent-Gate FinFETs for Low Power Logic Circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088.
  21. Bohr, Mark; Mistry, Kaizad (May 2011). "Intel's Revolutionary 22 nm Transistor Technology" (PDF). intel.com. Retrieved April 18, 2018.
  22. Grabham, Dan (May 6, 2011). "Intel's Tri-Gate transistors: everything you need to know". TechRadar. Retrieved April 19, 2018.
  23. Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond". IEEE Micro. 37 (6): 20–29. doi:10.1109/MM.2017.4241347. The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel’s 22-nm technology in 2011.
  24. Intel 22nm 3-D Tri-Gate Transistor Technology
  25. 1 2 "History: 2010s". SK Hynix . Retrieved 8 July 2019.
  26. "16/12nm Technology". TSMC . Retrieved 30 June 2019.
  27. 1 2 "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware . 11 April 2013. Retrieved 21 June 2019.
  28. 1 2 "7nm Technology". TSMC . Retrieved 30 June 2019.
  29. Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". www.anandtech.com. Retrieved 2019-05-31.
  30. Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com

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