Floating-gate MOSFET

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The floating-gate MOSFET (FGMOS), also known as a floating-gate transistor, is a type of MOSFET (metal-oxide-semiconductor field-effect transistor) where the gate is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify the amount of charge stored in the FG.


The FGMOS is commonly used as a floating-gate memory cell, the digital storage element in EPROM, EEPROM and flash memory technologies. Other uses of the FGMOS include a neuronal computational element in neural networks, [1] [2] analog storage element, [1] digital potentiometers and single-transistor DACs.


The first MOSFET was invented by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959, and presented in 1960. [3] The first report of a floating-gate MOSFET (FGMOS) was later made by Dawon Kahng and Simon Min Sze at Bell Labs, and dates from 1967. [4] The earliest practical application of FGMOS was floating-gate memory cells, which Kahng and Sze proposed could be used to produce reprogrammable ROM (read-only memory). [5] The first application of FGMOS was digital semiconductor memory, to store nonvolatile data in EPROM, EEPROM and flash memory. [6]

In 1989, Intel employed the FGMOS as an analog nonvolatile memory element in its electrically trainable artificial neural network (ETANN) chip, [2] demonstrating the potential of using FGMOS devices for applications other than digital memory.

Three research accomplishments laid the groundwork for much of the current FGMOS circuit development:

  1. Thomsen and Brooke's demonstration and use of electron tunneling in a standard CMOS double-poly process [7] allowed many researchers to investigate FGMOS circuits concepts without requiring access to specialized fabrication processes.
  2. The νMOS, or neuron-MOS, circuit approach by Shibata and Ohmi [8] provided the initial inspiration and framework to use capacitors for linear computations. These researchers concentrated on the FG circuit properties instead of the device properties, and used either UV light to equalize charge, or simulated FG elements by opening and closing MOSFET switches.
  3. Carver Mead's adaptive retina [1] gave the first example of using continuously-operating FG programming/erasing techniques, in this case UV light, as the backbone of an adaptive circuit technology.


A cross-section of a floating-gate transistor Floating gate transistor-en.svg
A cross-section of a floating-gate transistor

An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. A number of secondary gates or inputs are then deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a floating node.

For applications where the charge of the FG needs to be modified, a pair of small extra transistors are added to each FGMOS transistor to conduct the injection and tunneling operations. The gates of every transistor are connected together; the tunneling transistor has its source, drain and bulk terminals interconnected to create a capacitive tunneling structure. The injection transistor is connected normally and specific voltages are applied to create hot carriers that are then injected via an electric field into the floating gate.

FGMOS transistor for purely capacitive use can be fabricated on N or P versions. [9] For charge modification applications, the tunneling transistor (and therefore the operating FGMOS) needs to be embedded into a well, hence the technology dictates the type of FGMOS that can be fabricated.


Large signal DC

The equations modeling the DC operation of the FGMOS can be derived from the equations that describe the operation of the MOS transistor used to build the FGMOS. If it is possible to determine the voltage at the FG of an FGMOS device, it is then possible to express its drain to source current using standard MOS transistor models. Therefore, to derive a set of equations that model the large signal operation of an FGMOS device, it is necessary to find the relationship between its effective input voltages and the voltage at its FG.

Small signal

An N-input FGMOS device has N−1 more terminals than a MOS transistor, and therefore, N+2 small signal parameters can be defined: N effective input transconductances, an output transconductance and a bulk transconductance. Respectively:

where is the total capacitance seen by the floating gate. These equations show two drawbacks of the FGMOS compared with the MOS transistor:


Under normal conditions, a floating node in a circuit represents an error because its initial condition is unknown unless it is somehow fixed. This generates two problems: first, it is not easy to simulate these circuits; and second, an unknown amount of charge might stay trapped at the floating gate during the fabrication process which will result in an unknown initial condition for the FG voltage.

Among the many solutions proposed for the computer simulation, one of the most promising methods is an Initial Transient Analysis (ITA) proposed by Rodriguez-Villegas, [10] where the FGs are set to zero volts or a previously known voltage based on the measurement of the charge trapped in the FG after the fabrication process. A transient analysis is then run with the supply voltages set to their final values, letting the outputs evolve normally. The values of the FGs can then be extracted and used for posterior small-signal simulations, connecting a voltage supply with the initial FG value to the floating gate using a very-high-value inductor.


The usage and applications of the FGMOS can be broadly classified in two cases. If the charge in the floating gate is not modified during the circuit usage, the operation is capacitively coupled.

In the capacitively coupled regime of operation, the net charge in the floating gate is not modified. Examples of application for this regime are single transistor adders, DACs, multipliers and logic functions, variable threshold inverters,

Using the FGMOS as a programmable charge element, it is commonly used for non-volatile storage such as flash, EPROM and EEPROM memory. In this context, floating-gate MOSFETs are useful because of their ability to store an electrical charge for extended periods of time without a connection to a power supply. Other applications of the FGMOS are neuronal computational element in neural networks, analog storage element and e-pots.

See also

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  1. 1 2 3 Mead, Carver A.; Ismail, Mohammed, eds. (May 8, 1989). Analog VLSI Implementation of Neural Systems (PDF). The Kluwer International Series in Engineering and Computer Science. 80. Norwell, MA: Kluwer Academic Publishers. doi:10.1007/978-1-4613-1639-8. ISBN   978-1-4613-1639-8.
  2. 1 2 M. Holler, S. Tam, H. Castro, and R. Benson, "An electrically trainable artificial neural network with 10240 'floating gate' synapses", Proceedings of the International Joint Conference on Neural Networks, Washington, D.C., vol. II, 1989, pp. 191–196
  3. "1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum.
  4. Kahng, Dawon; Sze, Simon Min (1967). "A floating gate and its application to memory devices". The Bell System Technical Journal . 46 (6): 1288–1295. doi:10.1002/j.1538-7305.1967.tb01738.x.
  5. "1971: Reusable semiconductor ROM introduced". Computer History Museum . Retrieved 19 June 2019.
  6. Bez, R.; Pirovano, A. (2019). Advances in Non-Volatile Memory and Storage Technology. Woodhead Publishing. ISBN   9780081025857.
  7. A. Thomsen and M.A. Brooke, "A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process," IEEE Electron Device Letters, vol. 12, 1991, pp. 111-113
  8. T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations", IEEE Transactions on Electron Devices, vol. 39, no. 6, 1992, pp. 1444–1455
  9. Janwadkar, Sudhanshu (2017-10-24). "Fabrication of Floating Gate MOS (FLOTOX)". www.slideshare.net.
  10. Rodriguez-Villegas, Esther. Low Power and Low Voltage Circuit Design with the FGMOS Transistor