List of Intel CPU microarchitectures

Last updated

The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick–tock model and Process–architecture–optimization model.

Contents

x86 microarchitectures

x86 microarchitectures
YearMicro-architecturePipeline stagesMax
Clock

[MHz]

Process node

[nm]

1978 8086 (8086, 8088)25 3000
1982 186 (80186, 80188)225
1982 286 (80286)325 1500
1985 386 (80386)333
1989 486 (80486)5100 1000
1993 P5 (Pentium)5200 800, 600, 350
1995 P6 (Pentium Pro, Pentium II)14 (17 with load & store/retire)450 500, 350, 250
1997 P5 (Pentium MMX)6233350
1999 P6 (Pentium III)12 (15 with load & store/retire)1400250, 180, 130
2000 NetBurst  (Pentium 4)
(Willamette)
20 unified with branch prediction2000180
2002NetBurst (Pentium 4)
(Northwood, Gallatin)
3466130
2003 Pentium M (Banias, Dothan)
Enhanced Pentium M (Yonah)
10 (12 with fetch/retire)2333130, 90, 65
2004NetBurst (Pentium 4, Pentium D)
(Prescott)
31 unified with branch prediction380090, 65
2006 Intel Core 12 (14 with fetch/retire)300065
2007 Penryn (die shrink)3333 45
2008 Nehalem 20 unified (14 without miss prediction)3600
Bonnell 16 (20 with prediction miss)2100
2010 Westmere (die shrink)20 unified (14 without miss prediction)3866 32
2011 Saltwell (die shrink)16 (20 with prediction miss)2130
Sandy Bridge 14 (16 with fetch/retire)4000
2012 Ivy Bridge (die shrink)4100 22
2013 Silvermont 14–17 (16–19 with fetch/retire)2670
Haswell 14 (16 with fetch/retire)4400
2014 Broadwell (die shrink)3700 14
2015 Airmont (die shrink)14–17 (16–19 with fetch/retire)2640
Skylake 14 (16 with fetch/retire)5200
2016 Goldmont 20 unified with branch prediction2600
2017 Goldmont Plus  ? 20 unified with branch prediction ?2800
2018 Palm Cove 14 (16 with fetch/retire)3200 10
2019 Sunny Cove 14–20 (misprediction)4100
2020 Tremont 3300
Willow Cove 5300
2021 Cypress Cove 145200 14
Golden Cove 7
Gracemont
Note: Atom microarchitectures are in Italic

16-bit

8086
first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer.
186
included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
286
first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.

32-bit (IA-32)

i386
first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
i486
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
P5
original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
P6
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
NetBurst
commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

64-bit (x86-64)

Core
reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
Nehalem
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Sandy Bridge
32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007. [1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers.
  • Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.
Haswell
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
Skylake
14 nm microarchitecture, released August 5, 2015.
  • Kaby Lake: successor to Skylake, released in August 2016, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
    • Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes) [2]
    • Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities) [2]
  • Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for AVX-512 instruction set.
  • Coffee Lake: successor to Kaby Lake, using 14+ nm process, released in October 2017
  • Cascade Lake: server and high-end desktop successor to Kaby Lake-X and Skylake-X, using 14 nm process, released in April 2019
  • Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019 [3]
  • Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020 [4] [5]
Palm Cove
After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes. [6] [7]
Successor to Skylake (canceled), includes the AVX-512 instruction set. [8] [9]
  • Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019. [10]
Sunny Cove
Successor to the Palm Cove core, first core to include hardware acceleration for SHA hashing algorithms. [11]
  • Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
  • Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in performance cores (P-cores) of Lakefield processors. [12]
  • Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021 [4] [13]
Cypress Cove
Backport of Sunny Cove to Intel's 14nm process
Willow Cove
Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem. [17]
  • Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020
Golden Cove
Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions. [18]
  • Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF), [19] to be released on November 19, 2021. [20] Golden Cove is used in P-cores of Alder Lake processors. [21]
  • Sapphire Rapids: server-only, successor to Ice Lake-SP, also uses Intel 7 process. [19] [22]

x86 ULV (Atom)

Bonnell
45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
Silvermont
22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
Goldmont
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016. [23] [24]
  • Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.
Tremont
10 nm Atom microarchitecture iteration after Goldmont Plus. [25]
  • Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors. [12]
Gracemont
Intel 7 process [19] Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.
  • Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, to be released on November 19, 2021. Gracemont is used in E-cores of Alder Lake processors. [21]

Other microarchitectures

IA-64 (Itanium)

Merced
original Itanium microarchitecture. Used only in the first Itanium microprocessors.
McKinley
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
Montecito
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
Tukwila
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
Poulson
Itanium processor featuring a new microarchitecture. [26]
Kittson
the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.

Miscellaneous

XScale
a microarchitecture implementing the ARM architecture instruction set.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).

Roadmap

Pentium 4 / Core lines

Pentium 4 / Core roadmap
Fabrication
process
Micro-
architecture
Code
names
Core i
generation
Release
date
Processors
DesktopMobileEnthusiast/WS2P
Server/WS
4P/8P
Server
180 nm P6,
NetBurst
WillametteN/A2000-11-20WillametteFoster
130 nm Northwood/
Mobile Pentium 4
Banias
2002-01-07NorthwoodNorthwood Mobile
Banias
Northwood-XEPrestonia
Gallatin
90 nm Prescott
Dothan
2004-02-01Prescott
Smithfield
Dothan
Prescott 2M-XE
Smithfield-XE
Nocona
Irwindale
Paxville
Cranford
Potomac
65 nm Cedar Mill
Yonah
Presler
2006-01-05 Cedar Mill
Presler
Yonah Presler-XE Dempsey
Sossaman
Tulsa
Core Merom [27] 2006-07-27
[28] [29]
Conroe Merom Kentsfield Woodcrest
Clovertown
Tigerton
45 nm Penryn 2007-11-11
[30]
Wolfdale Penryn Yorkfield Harpertown Dunnington
Nehalem Nehalem Previous [31] 2008-11-17
[32]
Lynnfield Clarksfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01-04
[33] [34]
Clarkdale Arrandale Gulftown Westmere-EP Westmere-EX
Sandy
Bridge
Sandy Bridge 22011-01-09
[35]
Sandy Bridge Sandy Bridge-M Sandy Bridge-E Sandy Bridge-EP [36]
22 nm Ivy Bridge 32012-04-29 Ivy Bridge Ivy Bridge-M Ivy Bridge-E
[37]
Ivy Bridge-EP
[38]
Ivy Bridge-EX
[38]
Haswell Haswell 42013-06-02Haswell-DT
[39]
Haswell-MB
(37–57W TDP, PGA package)
Haswell-H
(47W TDP, BGA package)
Haswell-ULP/ULX
(11.5–15W TDP) [39]
Haswell-EHaswell-EPHaswell-EX
Devil's
Canyon
2014-06Haswell-DTN/A
14 nm Broadwell 52014-09-05Broadwell-DTBroadwell-H (37–47W TDP)
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP)
Broadwell-E Broadwell-EP
[40]
Broadwell-EX
[40]
Skylake [lower-alpha 1] Skylake 62015-08-05
[41]
Skylake-SSkylake-H (35–45W TDP)
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP)
Skylake-X [42]
Skylake-W
Skylake-SP
(formerly Skylake-EP/-EX) [43]
Kaby Lake 7 / 82016-10Kaby Lake-SKaby Lake-G (65–100W TDP)
Kaby Lake-H (35–45W TDP)
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP)
Kaby Lake-X
[42]
N/A
Coffee Lake 8 / 92017-10
[44]
Coffee Lake-SCoffee Lake-B (65W TDP)
Coffee Lake-H (35–45W TDP)
Coffee Lake-U (15–28W TDP)
N/A
Whiskey Lake 82018-08-28N/AWhiskey Lake-U (15W TDP)
Amber Lake 8 / 10Amber Lake-Y (5–7W TDP)
Cascade Lake N/A2019-04-02N/ACascade Lake-X
Cascade Lake-W
Cascade Lake-SP
Cascade Lake-SP
Comet Lake 102019-09 [lower-alpha 2] Comet Lake-SComet Lake-H (45W TDP)
Comet Lake-U (15W TDP) [45]
Comet Lake-Y (7W TDP) [45]
N/A
Cooper Lake N/A2020-06N/A [46] [47] Cooper Lake-SP
Cypress Cove [48] [49] Rocket Lake 112021-03Rocket Lake-SN/A
10 nm Palm Cove Cannon Lake 82018-05 [lower-alpha 2] N/ACannon Lake-U (15W TDP)N/A
Sunny Cove [50] Ice Lake 102019-09 (mobile) [lower-alpha 2]
2021-04 (server)
N/AIce Lake-U (15–28W TDP) [51]
Ice Lake-Y (9W TDP) [51]
N/AIce Lake-SP [52]
Willow Cove Tiger Lake 112020-09N/ATiger Lake-H (45W TDP)
Tiger Lake-H35 (28–35W TDP)
Tiger Lake-UP3 (12–28W TDP)
Tiger Lake-UP4 (7–15W TDP)
N/A
Intel 7 [19] Golden Cove Alder Lake
(hybrid)
122021 [16] [53] TBA Sapphire RapidsSP [54]
Intel 4 [19] TBA Meteor Lake TBA2023 [55] TBAGranite RapidsSP
Fabrication
process
Micro-
architecture
CodenamesCore i
generation
Release
date
DesktopMobileEnthusiast/
WS
2P
Server/WS
4P/8P
Server
Processors
  1. Cascade Lake and Cooper Lake microprocessors have additional instructions that enable Intel Deep Learning Boost.
  2. 1 2 3 retail availability

Atom lines [56]

Atom roadmap
Fabri-
cation
process
Micro-
archi-
tecture
Release
date
Processors/SoCs
MID, smartphoneTabletNetbookNettopEmbeddedServerCommunicationCE
45 nm Bonnell 2008 Silverthorne N/A Diamondville Tunnel Creek,
Stellarton
N/A Sodaville
2010 Lincroft Pineview Groveland
32 nm Saltwell 2011Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)
Clover Trail (Cloverview)Cedar Trail (Cedarview)Un­known Centerton & BriarwoodUn­known Berryville
22 nm Silvermont 2013Merrifield (Tangier), [57] Slayton,
Moorefield (Anniedale) [58]
Bay Trail-T
(Valleyview)
Bay Trail-M
(Valleyview)
Bay Trail-D
(Valleyview)
Bay Trail-I
(Valleyview)
AvotonRangeleyUn­known
14 nm [56] Airmont 2014Binghamton & RivertonCherry Trail-T (Cherryview) [59] Braswell [60] Denverton Cancelled cross.svgCancelledUn­knownUn­known
Goldmont
[61]
2016Broxton Cancelled cross.svgCancelledWillow Trail Cancelled cross.svgCancelled
Apollo Lake
Apollo Lake [62] Denverton [63] Un­knownUn­known
Goldmont
Plus
[64]
2017Un­knownUn­known Gemini Lake [65]
Gemini Lake Refresh [66]
Un­knownUn­knownUn­known
10 nm Tremont [25] 2020Un­knownLakefield (hybrid)Lakefield (hybrid)
Elkhart Lake [67]
Jasper Lake [68]
Jacobsville
Snow Ridge [69]
Un­knownUn­known
Intel 7 Gracemont [70] 2021N/AGrand Ridge

See also

Related Research Articles

Hyper-threading Proprietary simultaneous multithreading implementation by Intel

Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations performed on x86 microprocessors. It was introduced on Xeon server processors in February 2002 and on Pentium 4 desktop processors in November 2002. Since then, Intel has included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.

The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2004, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.

As of 2020, the x86 architecture is used in most high end compute-intensive computers, including cloud computing, servers, workstations, and many less powerful computers, including personal computer desktops and laptops. The ARM architecture is used in most other product categories, especially high-volume battery powered mobile devices such as smartphones and tablet computers.

Pentium Brand of microprocessors produced by Intel

Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel. The original Pentium was released in 1993. After that, the Pentium II and Pentium III were released.

Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick–tock is a model that refreshes one side of a binary system each release cycle.

Intel Core Mid-range to high-end central processing units

Intel Core are streamlined midrange consumer, workstation and enthusiast computers central processing units (CPU) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.

Skylake (microarchitecture) CPU microarchitecture by Intel

Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a "tock" in Intel's "tick–tock" manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Cannon Lake, Whiskey Lake, and Comet Lake CPUs.

Cannon Lake is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture. As a die shrink, Cannon Lake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set.

LGA 1151 Intel microprocessor compatible socket

LGA 1151, also known as Socket H4, is an Intel microprocessor compatible socket which comes in two distinct versions: the first revision which supports both Intel's Skylake and Kaby Lake CPUs, and the second revision which supports Coffee Lake CPUs exclusively.

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core.

Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's previous "tick–tock" manufacturing and design model, Kaby Lake represents the optimized step of the newer process–architecture–optimization model. Kaby Lake began shipping to manufacturers and OEMs in the second quarter of 2016, and mobile chips have started shipping while Kaby Lake (desktop) chips were officially launched in January 2017.

Ice Lake is Intel's codename for the 10th generation Intel Core mobile and 3rd generation Xeon Scalable server processors based on the new Sunny Cove microarchitecture. Ice Lake represents an Architecture step in Intel's Process-Architecture-Optimization model. Produced on the second generation of Intel's 10 nm process, 10 nm+, Ice Lake is Intel's second microarchitecture to be manufactured on the 10 nm process, following the limited launch of Cannon Lake in 2018. However, Intel altered their naming scheme in 2020 for the 10 nm process. In this new naming scheme, Ice Lake's manufacturing process is called simply 10 nm, without any appended pluses.

Coffee Lake Eighth-generation Intel Core microprocessor family

Coffee Lake is Intel's codename for its eighth generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Coffee Lake processors introduced i5 and i7 CPUs featuring six cores and Core i3 CPUs with four cores and no hyperthreading.

Epyc

EPYC is a brand of x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using Infinity Fabric interchip interconnect.

Goldmont Plus is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel. The Gemini Lake platform with 14 nm Goldmont Plus core was officially launched on December 11, 2017. Intel launched Gemini Lake Refresh platform on November 4, 2019.

Sunny Cove is a codename for a CPU microarchitecture developed by Intel, first released in September 2019. It succeeds the Palm Cove microarchitecture and is fabricated using Intel's 10 nm process node. The microarchitecture is implemented in 10th-generation Intel Core processors for mobile and third generation Xeon scalable server processors. 10th-generation Intel Core mobile processors were released in September 2019, while the Xeon server processors were released in April 6, 2021.

Tremont is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel, it is the successor to Goldmont Plus. Intel officially launched Elkhart Lake platform with 10nm Tremont core on September 23, 2020. Intel officially launched Jasper Lake platform with 10nm Tremont core on January 11, 2021.

Gracemont is an upcoming microarchitecture for low-power processors used in systems on a chip (SoCs) made by Intel, and is the successor to Tremont. Like its predecessor, it will also be implemented as low-power cores in a hybrid design of the upcoming Alder Lake processors.

Willow Cove is a codename for a CPU microarchitecture developed by Intel and released on September 2020. Willow Cove is the successor to the Sunny Cove microarchitecture, and is fabricated using Intel's enhanced 10 nm process node called 10 nm SuperFin (10SF). The microarchitecture powers 11th-generation Intel Core mobile processors.

Golden Cove is a codename for a CPU microarchitecture developed by Intel and scheduled to be released in 2021. It will succeed three microarchitectures: Sunny Cove, Willow Cove, and Cypress Cove. It will be fabricated using Intel's 7 nm class process node called Intel 7, previously referred to as 10 nm Enhanced SuperFin (10ESF).

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