NetBurst (microarchitecture)

Last updated

NetBurst
General information
LaunchedNovember 20, 2000;20 years ago (November 20, 2000)
Performance
Max. CPU clock rate 267 MHz to 3.8 GHz
FSB speeds400 MT/s to 1066 MT/s
Cache
L1 cache 8 KB to 16 KB per core
L2 cache128 KB to 2048 KB
L3 cache4 MB to 16 MB shared
Architecture and classification
ArchitectureNetBurst x86
Instructions x86, x86-64 (some)
Extensions
Physical specifications
Transistors
Cores
  • 1-2 (2-4 Threads w/ HT)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Celeron D Series
  • Pentium 4 Series
  • Pentium D Series
  • Xeon Series
History
Predecessor P6
Successor Intel Core
P7 Itanium(IA-64)

The NetBurst microarchitecture, [1] [2] called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2004, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.

Contents

NetBurst was replaced with the Core microarchitecture based on P6, released in July 2006.

Technology

The NetBurst microarchitecture includes features such as Hyper-threading, Hyper Pipelined Technology, Rapid Execution Engine, Execution Trace Cache, and replay system which all were introduced for the first time in this particular microarchitecture, and some never appeared again afterwards.

Hyper-threading

Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 microprocessors. Intel introduced it with NetBurst processors in 2002. Later Intel reintroduced it in the Nehalem microarchitecture after its absence in the Core 2.

Quad-Pumped Front-Side Bus

The Northwood and Willamette cores feature an external Front Side Bus (FSB) that runs at 100 MHz which transfers four bits per clock cycle, thus having an effective speed of 400 MHz. Later revisions of the Northwood core, along with the Prescott core (and derivatives) have an effective 800 MHz front-side bus (200 MHz quad pumped).

Hyper-Pipelined Technology

The Wilamette and Northwood cores contain a 20-stage instruction pipeline. This is a significant increase in the number of stages compared to the Pentium III, which had only 10 stages in its pipeline. The Prescott core increased the length of the pipeline to 31 stages. A drawback of longer pipelines is the increase in the number of stages that need to be traced back in the event that the branch misprediction, increasing the penalty of said misprediction. To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reduces branch mispredictions by 33% over Pentium III. [3] In reality, the longer pipeline resulted in reduced efficiency through a lower number of instructions per clock (IPC) executed as high enough clock speeds were not able to be reached to offset lost performance due to larger than expected increase in power consumption and heat.

Rapid Execution Engine

With this technology, the two arithmetic logic units (ALUs) in the core of the CPU are double-pumped, meaning that they actually operate at twice the core clock frequency. For example, in a 3.8 GHz processor, the ALUs will effectively be operating at 7.6 GHz. The reason behind this is to generally make up for the low IPC count; additionally this considerably enhances the integer performance of the CPU. Intel also replaced the high-speed barrel shifter with a shift/rotate execution unit that operates at the same frequency as the CPU core. The downside is that certain instructions are now much slower (relatively and absolutely) than before, making optimization for multiple target CPUs difficult. An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the i386, including the main competitor processor, Athlon.

Execution Trace Cache

Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache. It stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving considerable time. Moreover, the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution. [4] Intel later introduced a similar but simpler concept with Sandy Bridge called micro-operation cache (UOP cache).

Replay system

The replay system is a subsystem within the Intel Pentium 4 processor to catch operations that have been mistakenly sent for execution by the processor's scheduler. Operations caught by the replay system are then re-executed in a loop until the conditions necessary for their proper execution have been fulfilled.

Branch prediction hints

The Intel NetBurst architecture allows branch prediction hints to be inserted into the code to tell whether the static prediction should be taken or not taken, while this feature was abandoned in later Intel processors. According to Intel, NetBurst's branch prediction algorithm is 33% better than the one in P6. [5] [6]

Scaling-up issues

Despite these enhancements, the NetBurst architecture created obstacles for engineers trying to scale up its performance. With this microarchitecture, Intel looked to attain clock speeds of 10 GHz, [7] but because of rising clock speeds, Intel faced increasing problems with keeping power dissipation within acceptable limits. Intel reached a speed barrier of 3.8 GHz in November 2004 but encountered problems trying to achieve even that. Intel abandoned NetBurst in 2006 after the heat problems became unacceptable and then developed the Core microarchitecture, inspired by the P6 Core of the Pentium Pro to the Tualatin Pentium III-S, and most directly the Pentium M.

Revisions

RevisionProcessor Brand(s)Pipeline stages
Willamette (180 nm)Celeron, Pentium 420
Northwood (130 nm)Celeron, Pentium 4, Pentium 4 HT20
Gallatin (130 nm)Pentium 4 HT Extreme Edition, Xeon20
Prescott (90 nm)Celeron D, Pentium 4, Pentium 4 HT,
Pentium 4 Extreme Edition
31
Cedar Mill (65 nm)Celeron D, Pentium 431
Smithfield (90 nm)Pentium D31
Presler (65 nm)Pentium D31

Intel replaced the original Willamette core with a redesigned version of the NetBurst microarchitecture called Northwood in January 2002. The Northwood design combined an increased cache size, a smaller 130 nm fabrication process, and Hyper-threading (although initially all models but the 3.06 GHz model had this feature disabled) to produce a more modern, higher-performing version of the NetBurst microarchitecture.

In February 2004, Intel introduced Prescott, a more radical revision of the microarchitecture. The Prescott core was produced on a 90 nm process, and included several major design changes, including the addition of an even larger cache (from 512 KB in the Northwood to 1 MB, and 2 MB in Prescott 2M), a much deeper instruction pipeline (31 stages as compared to 20 in the Northwood), a heavily improved branch predictor, the introduction of the SSE3 instructions, and later, the implementation of Intel 64, Intel's branding for their compatible implementation of the x86-64 64-bit version of the x86 microarchitecture (as with hyper-threading, all Prescott chips branded Pentium 4 HT have hardware to support this feature, but it was initially only enabled on the high-end Xeon processors, before being officially introduced in processors with the Pentium trademark). Power consumption and heat dissipation also became major issues with Prescott, which quickly became the hottest-running, and most power-hungry, of Intel's single-core x86 and x86-64 processors. Power and heat concerns prevented Intel from releasing a Prescott clocked above 3.8 GHz, along with a mobile version of the core clocked above 3.46 GHz.

Intel also released a dual-core processor based on the NetBurst microarchitecture branded Pentium D. The first Pentium D core was codenamed Smithfield, which is actually two Prescott cores in a single die, and later Presler, which consists of two Cedar Mill cores on two separate dies (Cedar Mill being the 65 nm die-shrink of Prescott).

Roadmap

Successor

Intel had Netburst based successors in development called Tejas and Jayhawk with between 40 and 50 pipeline stages, but ultimately decided to replace NetBurst with the Core microarchitecture, [8] [9] released in July 2006; these successors were more directly derived from 1995's Pentium Pro (P6 microarchitecture). August 8, 2008 marked the end of Intel NetBurst based processors. [10] The reason for NetBurst's abandonment was the severe heat problems caused by high clock speeds. While some Core- and Nehalem-based processors have higher TDPs, most processors are multi-core, so each core gives off a fraction of the maximum TDP, and the highest-clocked Core-based single-core processors give off a maximum of 27 W of heat. The fastest-clocked desktop Pentium 4 processors (single-core) had TDPs of 115 W, compared to 88 W for the fastest clocked mobile versions. Although, with the introduction of new steppings, TDPs for some models were eventually lowered.

The Nehalem microarchitecture, the successor to the Core microarchitecture, was actually supposed to be an evolution of NetBurst according to Intel roadmaps dating back to 2000. But due to NetBurst's abandonment, Nehalem is now a completely different project, but has some similarities with NetBurst. Nehalem reimplements the Hyper-threading Technology first introduced in the 3.06 GHz Northwood core of Pentium 4. Nehalem also implements an L3 cache in processors based on it. For a consumer processor implementation, an L3 cache was first used in the Gallatin core of Pentium 4 Extreme Edition, but was oddly missing from Prescott 2M core of the same brand.

NetBurst-based chips

See also

Related Research Articles

Celeron Brand name by Intel

Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers.

Hyper-threading Proprietary simultaneous multithreading implementation by Intel

Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations performed on x86 microprocessors. It was introduced on Xeon server processors in February 2002 and on Pentium 4 desktop processors in November 2002. Since then, Intel has included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.

Pentium 4 Brand by Intel

Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 2000 until May 21, 2010.

Tejas was a code name for Intel's microprocessor, which was to be a successor to the latest Pentium 4 with the Prescott core and was sometimes referred to as Pentium V. Jayhawk was a code name for its Xeon counterpart. The cancellation of the processors in May 2004 underscored Intel's historical transition of its focus on single-core processors to multi-core processors.

Xeon Line of Intel server processors

Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for ECC memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture. They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Quick Path Interconnect (QPI) bus.

Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading. SMT permits multiple independent threads of execution to better utilize the resources provided by modern processor architectures.

The Pentium D brand refers to two series of desktop dual-core 64-bit x86-64 microprocessors with the NetBurst microarchitecture, which is the dual-core variant of Pentium 4 "Prescott" manufactured by Intel. Each CPU comprised two dies, each containing a single core, residing next to each other on a multi-chip module package. The brand's first processor, codenamed Smithfield, was released by Intel on May 25, 2005. Nine months later, Intel introduced its successor, codenamed Presler, but without offering significant upgrades in design, still resulting in relatively high power consumption. By 2004, the NetBurst processors reached a clock speed barrier at 3.8 GHz due to a thermal limit exemplified by the Presler's 130 watt thermal design power. The future belonged to more energy efficient and slower clocked dual-core CPUs on a single die instead of two. The final shipment date of the dual die Presler chips was August 8, 2008, which marked the end of the Pentium D brand and also the NetBurst microarchitecture.

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from the P6 microarchitecture.

The Intel Core microarchitecture is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. It is based on the Yonah processor design and can be considered an iteration of the P6 microarchitecture introduced in 1995 with Pentium Pro. High power consumption and heat intensity, the resulting inability to effectively increase clock rate, and other shortcomings such as an inefficient pipeline were the primary reasons why Intel abandoned the NetBurst microarchitecture and switched to a different architectural design, delivering high efficiency through a small pipeline rather than high clock rates. The Core microarchitecture initially did not reach the clock rates of the NetBurst microarchitecture, even after moving to 45 nm lithography. However after many generations of successor microarchitectures which used Core as their basis, Intel managed to eventually surpass the clock rates of Netburst with the Devil's Canyon microarchitecture reaching a base frequency of 4 GHz and a maximum tested frequency of 4.4 GHz using 22 nm lithography.

Pentium Brand of microprocessors produced by Intel

Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel since 1993. In their form as of November 2011, Pentium processors are considered entry-level products that Intel rates as "two stars", meaning that they are above the low-end Atom and Celeron series, but below the faster Intel Core lineup, and workstation Xeon series.

Nehalem (microarchitecture)

Nehalem is the codename for an Intel processor microarchitecture released in November 2008. Nehalem was used in the first generation of the Intel Core processors. Nehalem is the successor to the older Core microarchitecture.

Pentium Dual-Core

The Pentium Dual-Core brand was used for mainstream x86-architecture microprocessors from Intel from 2006 to 2009 when it was renamed to Pentium. The processors are based on either the 32-bit Yonah or 64-bit Merom-2M, Allendale, and Wolfdale-3M core, targeted at mobile or desktop computers.

Conroe (microprocessor) Code name for several Intel processors

Conroe is the code name for many Intel processors sold as Core 2 Duo, Xeon, Pentium Dual-Core and Celeron. It was the first desktop processor to be based on the Core microarchitecture, replacing the NetBurst microarchitecture based Cedar Mill processor. It has product code 80557, which is shared with Allendale and Conroe-L that are very similar but have a smaller L2 cache. Conroe-L has only one processor core and a new CPUID model. The mobile version of Conroe is Merom, the dual-socket server version is Woodcrest, and the quad-core desktop version is Kentsfield. Conroe was replaced by the 45 nm Wolfdale processor.

Wolfdale (microprocessor)

Wolfdale is the code name for a processor from Intel that is sold in varying configurations as Core 2 Duo, Celeron, Pentium and Xeon. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. This replaced the Conroe processor with Wolfdale.

Yorkfield is the code name for some Intel processors sold as Core 2 Quad and Xeon. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23, replacing Kentsfield, the previous model.

Intel Core Mid-range to high-end central processing units

Intel Core are streamlined midrange consumer, workstation and enthusiast computers central processing units (CPU) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.

Goldmont Plus is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel. The Gemini Lake platform with 14 nm Goldmont Plus core was officially launched on December 11, 2017. Intel launched Gemini Lake Refresh platform on November 4, 2019.

References

  1. Carmean, Doug (Spring 2002). "The Intel Pentium 4 Processor" (PDF). Intel. Archived from the original (PDF) on April 19, 2018.
  2. "Replay: Unknown Features of the NetBurst Core". XbitLabs. March 6, 2016. Archived from the original on March 6, 2016.
  3. "The Trace Cache Branch Prediction Unit". Intel's New Pentium 4 Processor. Tom's Hardware. November 20, 2000. Retrieved April 30, 2021.
  4. "Entering The Execution Pipeline - Pentium 4's Trace Cache, Continued". Intel's New Pentium 4 Processor. Tom's Hardware. November 20, 2000. Retrieved April 30, 2021.
  5. Fog, Agner (December 1, 2016). "The microarchitecture of Intel, AMD and VIA CPUs" (PDF). p. 36. Retrieved March 22, 2017.
  6. Milenkovic, Milena; Milenkovic, Aleksandar; Kulick, Jeffrey. "Demystifying Intel Branch Predictors" (PDF).
  7. Shimpi, Anand Lal. "The future of Intel's manufacturing processes" . Retrieved April 4, 2018.
  8. "Intel says Adios to Tejas and Jayhawk chips". The Register .
  9. Goodwins, Rupert. "Intel cancels Tejas and Jayhawk". ZDNet. Retrieved August 21, 2019.
  10. Shilov, Anton (May 21, 2007). "The Era of Intel's NetBurst Micro-Architecture Comes to End". XbitLabs. Archived from the original on October 17, 2015. Retrieved November 29, 2015.