PHY

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RTL8201 Ethernet PHY chip Elitegroup 761GX-M754 - Realtek RTL8201CL-5493.jpg
RTL8201 Ethernet PHY chip
Texas Instruments DP83825 - 3mm x 3mm 3.3V PHY chip DP83825I smaller.png
Texas Instruments DP83825 - 3mm x 3mm 3.3V PHY chip

A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as an integrated circuit, required to implement physical layer functions of the OSI model in a network interface controller.

Contents

A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality. [1]

-PHY may also be used as a suffix to form a short name referencing a specific physical layer protocol, for example M-PHY.

Modular transceivers for fiber-optic communication (like the SFP family) complement a PHY chip and form the PMA sublayer.

Ethernet physical transceiver

Micrel KS8721CL - 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver Micrel KS8721CL on mainboard of Surf@home II-7778.jpg
Micrel KS8721CL - 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver

The Ethernet PHY is a component that operates at the physical layer of the OSI network model. It implements the physical layer portion of the Ethernet. Its purpose is to provide analog signal physical access to the link. It is usually interfaced with a Media Independent Interface (MII) to a MAC chip in a microcontroller or another system that takes care of the higher layer functions.

More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling. [2] The PHY usually does not handle MAC addressing, as that is the link layer's job. Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Common ethernet interfaces include fiber, or two to four copper pairs for data communication. However, there now exists a new interface, called Single Pair Ethernet (SPE), which is able to utilize a single pair of copper wires while still communicating at the intended speeds. Texas Instruments DP83TD510E [3] is an example of a PHY which uses SPE.

Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers, Texas Instruments DP838xx family [4] and offerings from Intel [5] and ICS. [6]

Other applications

Related Research Articles

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Fast Ethernet Ethernet standards that carry traffic at the nominal rate of 100 Mbit/s

In computer networking, Fast Ethernet physical layers carry traffic at the nominal rate of 100 Mbit/s. The prior Ethernet speed was 10 Mbit/s. Of the Fast Ethernet physical layers, 100BASE-TX is by far the most common.

Gigabit Ethernet

In computer networking, Gigabit Ethernet is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. The most popular variant 1000BASE-T is defined by the IEEE 802.3ab standard. It came into use in 1999, and has replaced Fast Ethernet in wired local networks due to its considerable speed improvement over Fast Ethernet, as well as its use of cables and equipment that are widely available, economical, and similar to previous standards.

In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer. This layer may be implemented by a PHY chip.

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10 Gigabit Attachment Unit Interface is a standard for extending the XGMII between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface".

The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet media access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission media.

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References

  1. Mauricio Arregoces; Maurizio Portolani (2003). Data Center Fundamentals. ISBN   9781587050237 . Retrieved 2015-11-18.
  2. "microcontroller - what is the difference between PHY and MAC chip - Electrical Engineering Stack Exchange". Electronics.stackexchange.com. 2013-07-11. Retrieved 2015-11-18.
  3. "DP83TD510E Ultra Low Power 802.3cg 10Base-T1L 10M Single Pair Ethernet PHY" (PDF). Texas Instruments. Retrieved 12 October 2020.
  4. "Ethernet PHYs". Texas Instruments. Retrieved 12 October 2020.
  5. Intel PHY controllers brochure
  6. osuosl.org - ICS1890 10Base-T/100Base-TX Integrated PHYceiver datasheet