SONOS

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SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"silicon dioxide"—"silicon", [1] :121 is a cross sectional structure of MOSFET (metal-oxide-semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977. [2] This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays. [3] It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material. [4] :Fig. 1 A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon"). [5] :137 [6] :66 Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia.

Contents

Description

Cross sectional drawing of a SONOS memory cell SONOS cell structure.svg
Cross sectional drawing of a SONOS memory cell

A SONOS memory cell is formed from a standard polysilicon N-channel MOSFET transistor with the addition of a small sliver of silicon nitride inserted inside the transistor's gate oxide. The sliver of nitride is non-conductive but contains a large number of charge trapping sites able to hold an electrostatic charge. The nitride layer is electrically isolated from the surrounding transistor, although charges stored on the nitride directly affect the conductivity of the underlying transistor channel. The oxide/nitride sandwich typically consists of a 2 nm thick oxide lower layer, a 5 nm thick silicon nitride middle layer, and a 5–10 nm oxide upper layer.

When the polysilicon control gate is biased positively, electrons from the transistor source and drain regions tunnel through the oxide layer and get trapped in the silicon nitride. This results in an energy barrier between the drain and the source, raising the threshold voltage Vt (the gate-source voltage necessary for current to flow through the transistor). The electrons can be removed again by applying a negative bias on the control gate.

A SONOS memory array is constructed by fabricating a grid of SONOS transistors which are connected by horizontal and vertical control lines (wordlines and bitlines) to peripheral circuitry such as address decoders and sense amplifiers. After storing or erasing the cell, the controller can measure the state of the cell by passing a small voltage across the source-drain nodes; if current flows the cell must be in the "no trapped electrons" state, which is considered a logical "1". If no current is seen the cell must be in the "trapped electrons" state, which is considered as "0" state. The needed voltages are normally about 2 V for the erased state, and around 4.5 V for the programmed state.

Comparison with Floating-Gate structure

Generally SONOS is very similar to traditional FG (floating gate) type memory cell, [1] :117 but hypothetically offers higher quality storage. This is due to the smooth homogeneity of the Si3N4 film compared with polycrystalline film which has tiny irregularities. Flash requires the construction of a very high-performance insulating barrier on the gate leads of its transistors, often requiring as many as nine different steps, whereas the oxide layering in SONOS can be more easily produced on existing lines and more easily combined with CMOS logic.

Additionally, traditional flash is less tolerant of oxide defects[ citation needed ] because a single shorting defect will discharge the entire polysilicon floating gate. The nitride in the SONOS structure is non-conductive, so a short only disturbs a localized patch of charge. Even with the introduction of new insulator technologies this has a definite "lower limit" around 7 to 12 nm, which means it is difficult for flash devices to scale smaller than about 45 nm linewidths. But, Intel-Micron group have realized 16 nm planar flash memory with traditional FG technology. [7] :13 [8] SONOS, on the other hand, requires a very thin layer of insulator in order to work, making the gate area smaller than flash. This allows SONOS to scale to smaller linewidth, with recent examples being produced on 40 nm fabs and claims that it will scale to 20 nm. [9] The linewidth is directly related to the overall storage of the resulting device, and indirectly related to the cost; in theory, SONOS' better scalability will result in higher capacity devices at lower costs.

Additionally, the voltage needed to bias the gate during writing is much smaller than in traditional flash. In order to write flash, a high voltage is first built up in a separate circuit known as a charge pump, which increases the input voltage to between 9 V to 20 V. This process takes some time, meaning that writing to a flash cell is much slower than reading, often between 100 and 1000 times slower. The pulse of high power also degrades the cells slightly, meaning that flash devices can only be written to between 10,000 and 100,000 times, depending on the type. SONOS devices require much lower write voltages, typically 5–8 V, and do not degrade in the same way. SONOS does suffer from the converse problem however, where electrons become strongly trapped in the ONO layer and cannot be removed again. Over long usage this can eventually lead to enough trapped electrons to permanently set the cell to the "0" state, similar to the problems in flash. However,[ citation needed ] in SONOS this requires on the order of a 100 thousands write/erase cycles, [10] 10 to 100 times worse compared with legacy FG memory cell. [11]

History

Background

The original MOSFET (metal-oxide-semiconductor field-effect transistor, or MOS transistor) was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in 1959, and demonstrated in 1960. [12] Kahng went on to invent the floating-gate MOSFET with Simon Min Sze at Bell Labs, and they proposed its use as a floating-gate (FG) memory cell, in 1967. [13] This was the first form of non-volatile memory based on the injection and storage of charges in a floating-gate MOSFET, [14] which later became the basis for EPROM (erasable PROM), EEPROM (electrically erasable PROM) and flash memory technologies. [15] [16]

In late 1967, a Sperry research team led by H.A. Richard Wegener, A.J. Lincoln and H.C. Pao invented the metal–nitride–oxide–semiconductor transistor (MNOS transistor), [17] a type of MOSFET in which the oxide layer is replaced by a double layer of nitride and oxide. [18] Nitride was used as a trapping layer instead of a floating gate, but its use was limited as it was considered inferior to a floating gate. [19] Charge trap (CT) memory was introduced with MNOS devices in the late 1960s. It had a device structure and operating principles similar to floating-gate (FG) memory, but the main difference is that the charges are stored in a conducting material (typically a doped polysilicon layer) in FG memory, whereas CT memory stored charges in localized traps within a dielectric layer (typically made of silicon nitride). [14]

Development

SONOS was first conceptualized in the 1960s. MONOS is realized in 1968 by Westinghouse Electric Corporation. [20] [21] In the early 1970s initial commercial devices were realized using PMOS transistors and a metal-nitride-oxide (MNOS) stack with a 45 nm nitride storage layer. These devices required up to 30V to operate. In 1977, P.C.Y. Chen of Fairchild Camera and Instrument introduced a SONOS cross sectional structured MOSFET with tunnel silicon dioxide of 30 Ångström thickness for EEPROM. [2] According to NCR Corporation's patent application in 1980, SONOS structure required +25 volts and −25 volts for writing and erasing, respectively. [22] It was improved to +12 V by PMOS-based MNOS (metal-nitride-oxide-semiconductor) structure. [23]

By the early 1980s, polysilicon NMOS-based structures were in use with operating voltages under 20 V. By the late 1980s and early 1990s PMOS SONOS structures were demonstrating program/erase voltages in the range of 5–12 volts. [24] On the other hand, in 1980, Intel realized highly reliable EEPROM with double layered polysilicon structure, which is named FLOTOX, [25] both for erase and write cycling endurance and for data retention term. [26] SONOS has been in the past produced by Philips Semiconductors, Spansion, Qimonda and Saifun Semiconductors.

Recent efforts

In 2002, AMD and Fujitsu, formed as Spansion in 2003 and later merged with Cypress Semiconductor in 2014, developed a SONOS-like MirrorBit technology based on the license from Saifun Semiconductors, Ltd.'s NROM technology. [27] [28] [29] As of 2011 Cypress Semiconductor developed SONOS memories for multiple processes, [30] and started to sell them as IP to embed in other devices. [31] UMC has already used SONOS since 2006 [32] and has licensed Cypress for 40 nm [33] and other nodes. Shanghai Huali Microelectronics Corporation (HLMC) has also announced [34] to be producing Cypress SONOS at 40 nm and 55 nm.

In 2006, Toshiba developed a new double tunneling layer technology with SONOS structure, which utilize Si9N10 silicon nitride. [35] [36] Toshiba also researches MONOS ("Metal-Oxide-Nitride-Oxide-Silicon") structure for their 20 nm node NAND gate type flash memories. [37] Renesas Electronics uses MONOS structure in 40 nm node era. [38] [39] :5 which is the result of collaboration with TSMC. [40]

While other companies still use FG (floating gate) structure. [41] :50 For example, GlobalFoundries use floating-gate-based split-gate SuperFlash ESF3 cell for their 40 nm products. [42] Some new structure for FG (floating gate) type flash memories are still intensively studied. [43] In 2016, GlobalFoundries developed FG-based 2.5V Embedded flash macro. [44] In 2017, Fujitsu announced to license FG-based ESF3/FLOTOX structure, [25] [26] which is originally developed by Intel in 1980, from Silicon Storage Technology for their embedded non-volatile memory solutions. [45] [46] [47] As of 2016, Intel-Micron group have disclosed that they stayed traditional FG technology in their 3-dimensional NAND flash memory. [7] They also use FG technology for 16 nm planar NAND flash. [8]

See also

Related Research Articles

Semiconductor device fabrication Manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

MOSFET Transistor used for amplifying or switching electronic signals.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of insulated-gate field-effect transistor (IGFET) that is fabricated by the controlled oxidation of a semiconductor, typically silicon. The voltage of the covered gate determines the electrical conductivity of the device; this ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in 1959. It is the basic building block of modern electronics, and the most frequently manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.

CMOS Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

Flash memory Electronic non-volatile computer storage device

Flash memory is an electronic (solid-state) non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory are named after the NAND and NOR logic gates. The individual flash memory cells, consisting of floating-gate MOSFETs, exhibit internal characteristics similar to those of the corresponding gates.

EEPROM nonvolatile memory comprising arrays of floating-gate transistors used in computers, microcontrollers &c. to store relatively small amounts of data but allowing individual bytes to be erased/reprogrammed in-circuit through special programming signals

EEPROM (also E2PROM) stands for electrically erasable programmable read-only memory and is a type of non-volatile memory used in computers, integrated in microcontrollers for smart cards and remote keyless systems, and other electronic devices to store relatively small amounts of data but allowing individual bytes to be erased and reprogrammed.

An EPROM, or erasable programmable read-only memory, is a type of programmable read-only memory (PROM) chip that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to strong ultraviolet light source. EPROMs are easily recognizable by the transparent fused quartz window in the top of the package, through which the silicon chip is visible, and which permits exposure to ultraviolet light during erasing.

In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

High-electron-mobility transistor

A high-electron-mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a field-effect transistor incorporating a junction between two materials with different band gaps as the channel instead of a doped region. A commonly used material combination is GaAs with AlGaAs, though there is wide variation, dependent on the application of the device. Devices incorporating more indium generally show better high-frequency performance, while in recent years, gallium nitride HEMTs have attracted attention due to their high-power performance. Like other FETs, HEMTs are used in integrated circuits as digital on-off switches. FETs can also be used as amplifiers for large amounts of current using a small voltage as a control signal. Both of these uses are made possible by the FET’s unique current–voltage characteristics. HEMT transistors are able to operate at higher frequencies than ordinary transistors, up to millimeter wave frequencies, and are used in high-frequency products such as cell phones, satellite television receivers, voltage converters, and radar equipment. They are widely used in satellite receivers, in low power amplifiers and in the defense industry.

FinFET type of transistor used in nanoelectronic integrated circuits

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS technology.

The floating-gate MOSFET (FGMOS), also known as a floating-gate transistor, is a type of MOSFET where the gate is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify the amount of charge stored in the FG.

Charge trap flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. It is a type of floating-gate MOSFET memory technology, but differs from the conventional floating-gate technology in that it uses a silicon nitride film to store electrons rather than the doped polycrystalline silicon typical of a floating-gate structure. This approach allows memory manufacturers to reduce manufacturing costs five ways:

  1. Fewer process steps are required to form a charge storage node
  2. Smaller process geometries can be used
  3. Multiple bits can be stored on a single flash memory cell.
  4. Improved reliability
  5. Higher yield since the charge trap is less susceptible to point defects in the tunnel oxide layer

Hot carrier injection (HCI) is a phenomenon in solid-state electronic devices where an electron or a “hole” gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The term "hot" refers to the effective temperature used to model carrier density, not to the overall temperature of the device. Since the charge carriers can become trapped in the gate dielectric of a MOS transistor, the switching characteristics of the transistor can be permanently changed. Hot-carrier injection is one of the mechanisms that adversely affects the reliability of semiconductors of solid-state devices.

In electronics, a self-aligned gate is a transistor manufacturing feature whereby a refractory gate electrode region of a MOSFET is used as a mask for the doping of the source and drain regions. This technique ensures that the gate will slightly overlap the edges of the source and drain.

Fujio Masuoka is a Japanese engineer, who has worked for Toshiba and Tohoku University, and is currently chief technical officer (CTO) of Unisantis Electronics. He is best known as the inventor of flash memory, including the development of both the NOR flash and NAND flash types in the 1980s. He also invented the first gate-all-around (GAA) MOSFET (GAAFET) transistor, an early non-planar 3D transistor, in 1988.

Polysilicon depletion effect is the phenomenon in which unwanted variation of threshold voltage of the MOSFET devices using polysilicon as gate material is observed, leading to unpredicted behavior of the electronic circuit. Polycrystalline silicon, also called polysilicon, is a material consisting of small silicon crystals. It differs from single-crystal silicon, used for electronics and solar cells, and from amorphous silicon, used for thin film devices and solar cells.

Dawon Kahng South Korean engineer

Dawon Kahng was a Korean-American electrical engineer and inventor, known for his work in solid-state electronics. He is best known for inventing the MOSFET, also known as the MOS transistor, with Mohamed Atalla in 1959. Atalla and Kahng developed both the PMOS and NMOS processes for MOSFET semiconductor device fabrication. The MOSFET is the most widely used type of transistor, and the basic element in most modern electronic equipment.

Field-effect transistor transistor that uses an electric field to control its electrical behaviour

The field-effect transistor (FET) is a type of transistor which uses an electric field to control the flow of current. FETs are devices with three terminals: source, gate, and drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source.

Memory cell (computing) part of computer memory

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 and reset to store a logic 0. Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

The metal–nitride–oxide–semiconductor or metal–nitride–oxide–silicon (MNOS) transistor is a type of MOSFET in which the oxide layer is replaced by a double layer of nitride and oxide. It is an alternative and supplement to the existing standard MOS technology, wherein the insulation employed is a nitride-oxide layer. It is used in non-volatile computer memory.

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