Self-aligned gate

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In electronics, a self-aligned gate is a transistor manufacturing feature whereby a refractory gate electrode region of a MOSFET (metal–oxide–semiconductor field-effect transistor) is used as a mask for the doping of the source and drain regions. This technique ensures that the gate will slightly overlap the edges of the source and drain.

Electronics physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter

Electronics comprises the physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter.

Transistor Basic electronics component

A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits.

MOSFET Transistor used for amplifying or switching electronic signals.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of field-effect transistor that is fabricated by the controlled oxidation of a semiconductor, typically silicon. It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET is the basic building block of modern electronics. Since its invention by Mohamed M. Atalla and Dawon Kahng at Bell Labs in November 1959, the MOSFET has become the most widely manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOS transistors manufactured between 1960 and 2018.


The use of self-aligned gates in MOS transistors is one of the key innovations that led to the large increase in computing power in the 1970s. Self-aligned gates are still used in most modern integrated circuit processes.

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny MOS transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Semiconductor device fabrication manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, particularly the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.


Diagram of a standard MOSFET Lateral mosfet.svg
Diagram of a standard MOSFET

The self-aligned gate is used to eliminate the need to align the gate electrode to the source and drain regions of a MOS transistor during the fabrication process. [1] With self-aligned gates, the parasitic overlap capacitances between gate and source, and gate and drain, are substantially reduced, leading to MOS transistors that are faster, smaller, and more reliable than transistors made without them. After the early experimentation with different gate materials (aluminum, molybdenum, amorphous silicon) the industry almost universally adopted self-aligned gates made with polycrystalline silicon, the so-called silicon-gate technology (SGT), which had many additional benefits over the reduction of parasitic capacitances. One important feature of SGT was that the silicon gate was entirely buried under top quality thermal oxide (one of the best insulators known), making it possible to create new device types, not feasible with conventional technology or with self-aligned gates made with other materials. Particularly important are charge-coupled devices (CCD), used for image sensors, and non-volatile memory devices using floating silicon-gate structures. These devices dramatically enlarged the range of functionality that could be achieved with solid state electronics.

Innovations that made self-aligned gate technology possible

Certain innovations were required in order to make self-aligned gates: [2]

Amorphous silicon non-crystalline silicon

Amorphous silicon (a-Si) is the non-crystalline form of silicon used for solar cells and thin-film transistors in LCDs.

Polycrystalline silicon high purity, polycrystalline form of silicon

Polycrystalline silicon, also called polysilicon or poly-Si, is a high purity, polycrystalline form of silicon, used as a raw material by the solar photovoltaic and electronics industry.

Photolithography, also called optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a photosensitive chemical photoresist on the substrate. A series of chemical treatments then either etches the exposure pattern into the material or enables deposition of a new material in the desired pattern upon the material underneath the photoresist. In complex integrated circuits, a CMOS wafer may go through the photolithographic cycle as many as 50 times.

Prior to these innovations, self-aligned gates had been demonstrated on metal-gate devices, but their real impact was on silicon-gate devices.

Metal gate

A metal gate, in the context of a lateral metal-oxide-semiconductor (MOS) stack, is just that—the gate material is made from a metal.


The first MOSFET was invented by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959. [3] [4] They used silicon as channel material and a non-self-aligned aluminium (Al) gate. [5] The aluminum-gate MOS process technology started with the definition and doping of the source and drain regions of MOS transistors, followed by the gate mask that defined the thin-oxide region of the transistors. With additional processing steps, an aluminum gate would then be formed over the thin-oxide region completing the device fabrication. Due to the inevitable misalignment of the gate mask with respect to the source and drain mask, it was necessary to have a fairly large overlap area between the gate region and the source and drain regions, to ensure that the thin-oxide region would bridge the source and drain, even under worst-case misalignment. This requirement resulted in gate-to-source and gate-to-drain parasitic capacitances that were large and variable from wafer to wafer, depending on the misalignment of the gate oxide mask with respect with the source and drain mask. The result was an undesirable spread in the speed of the integrated circuits produced, and a much lower speed than theoretically possible if the parasitic capacitances could be reduced to a minimum. The overlap capacitance with the most adverse consequences on performance was the gate-to-drain parasitic capacitance, Cgd, which, by the well-known Miller effect, augmented the gate-to-source capacitance of the transistor by Cgd multiplied by the gain of the circuit to which that transistor was a part. The impact was a considerable reduction in the switching speed of transistors.

In 1966, R.W. Bower realized that if the gate electrode was defined first, it would be possible not only to minimize the parasitic capacitances between gate and source and drain, but it would also make them insensitive to misalignment. He proposed a method in which the aluminum gate electrode itself was used as a mask to define the source and drain regions of the transistor. However, since aluminum could not withstand the high temperature required for the conventional doping of the source and drain junctions, Bower proposed to use ion implantation, a new doping technique still in development at Hughes Aircraft, his employer, and not yet available at other labs. While Bower’s idea was conceptually sound, in practice it did not work, because it was impossible to adequately passivate the transistors, and repair the radiation damage done to the silicon crystal structure by the ion implantation, since these two operations would have required temperatures in excess of the ones survivable by the aluminum gate. Thus his invention provided a proof of principle, but no commercial integrated circuit was ever produced with Bower’s method. A more refractory gate material was needed.

In 1967, John C. Sarace and collaborators at Bell Labs replaced the aluminum gate with an electrode made of vacuum-evaporated amorphous silicon and succeeded in building working self-aligned gate MOS transistors. However, the process, as described, was only a proof of principle, suitable only for the fabrication of discrete transistors and not for integrated circuits; and was not pursued any further by its investigators.

In 1968, the MOS industry was prevalently using aluminum gate transistors with high threshold voltage (HVT) and desired to have a low threshold voltage (LVT) MOS process in order to increase the speed and reduce the power dissipation of MOS integrated circuits. Low threshold voltage transistors with aluminum gate demanded the use of [100] silicon orientation, which however produced too low a threshold voltage for the parasitic MOS transistors (the MOS transistors created when aluminum over the field oxide would bridge two junctions). To increase the parasitic threshold voltage beyond the supply voltage, it was necessary to increase the N-type doping level in selected regions under the field oxide, and this was initially accomplished with the use of a so-called channel-stopper mask, and later with ion implantation.

Development of the silicon-gate technology at Fairchild

The SGT was the first process technology used to fabricate commercial MOS integrated circuits that was later widely adopted by the entire industry in the 1960s. In late 1967, Tom Klein, working at the Fairchild Semiconductor R&D Labs, and reporting to Les Vadasz, realized that the work function difference between heavily P-type doped silicon and N-type silicon was 1.1 volt lower than the work function difference between aluminum and the same N-type silicon. This meant that the threshold voltage of MOS transistors with silicon gate could be 1.1 volt lower than the threshold voltage of MOS transistors with aluminum gate fabricated on the same starting material. Therefore, one could use starting material with [111] silicon orientation and simultaneously achieve both an adequate parasitic threshold voltage and low threshold voltage transistors without the use of a channel-stopper mask or ion implantation under the field oxide. With P-type doped silicon gate it would therefore be possible not only to create self-aligned gate transistors but also a low threshold voltage process by using the same silicon orientation of the high threshold voltage process.

In February 1968, Federico Faggin joined Les Vadasz's group and was put in charge of the development of a low-threshold-voltage, self-aligned gate MOS process technology. Faggin's first task was to develop the precision etching solution for the amorphous silicon gate, and then he created the process architecture and the detailed processing steps to fabricate MOS ICs with silicon gate. He also invented the ‘buried contacts,’ a method to make direct contact between amorphous silicon and silicon junctions, without the use of metal, a technique that allowed a much higher circuit density, particularly for random logic circuits.

After validating and characterizing the process using a test pattern he designed, Faggin made the first working MOS silicon-gate transistors and test structures by April 1968. He then designed the first integrated circuit using silicon gate, the Fairchild 3708, an 8-bit analog multiplexer with decoding logic, that had the same functionality of the Fairchild 3705, a metal-gate production IC that Fairchild Semiconductor had difficulty making on account of its rather stringent specifications.

The availability of the 3708 in July 1968 provided also a platform to further improve the process during the following months, leading to the shipment of the first 3708 samples to customers in October 1968, and making it commercially available to the general market before the end of 1968. During the period, July to October 1968, Faggin added two additional critical steps to the process:

With silicon gate, the long-term reliability of MOS transistors soon reached the level of bipolar ICs removing one major obstacle to the wide adoption of MOS technology.

By the end of 1968 the silicon-gate technology had achieved impressive results. Although the 3708 was designed to have approximately the same area as the 3705 to facilitate using the same production tooling as the 3705, it could have been made considerably smaller. Nonetheless, it had superior performance compared with the 3705: it was 5 times faster, it had about 100 times less leakage current, and the on resistance of the large transistors making up the analog switches was 3 times lower.[ citation needed ] The silicon-gate technology (SGT) was also adopted by Intel at its founding (July 1968), and within a few years became the core technology for the fabrication of MOS integrated circuits worldwide, lasting to this day. Intel was also the first company to develop non-volatile memory using floating silicon-gate transistors.

Original documents on SGT


The self-aligned gate design was patented in 1969 by the team of Kerwin, Klein, and Sarace. [6] It was independently invented by Robert W. Bower (U.S. 3,472,712, issued October 14, 1969, filed October 27, 1966). The Bell Labs Kerwin et al. patent 3,475,234 was not filed until March 27, 1967, several months after R. W. Bower and H. D. Dill had published and presented the first publication of this work at the International Electron Device Meeting, Washington, D.C. in 1966. [7]

However, in a legal action involving Bower and Dill, the Third Circuit Court of Appeals determined that Kerwin, Klein and Sarace were the true inventors of the self-aligned silicon gate transistor. On that basis, they were awarded the basic patent US 3,475,234 (the US patent system awards the basic patent to the party that first makes the invention, not the party that first files a patent application, per rules at that time). Bower's work described the self-aligned-gate MOSFET, made with both aluminum and polysilicon gates. It used both ion implantation and diffusion to form the source and drain using the gate electrode as the mask to define the source and drain regions. The Bell Labs team attended this meeting of the IEDM in 1966, and they discussed this work with Bower after his presentation in 1966. Bower believed he had first made the self-aligned gate using aluminum as the gate and, before presentation in 1966, made the device using polysilicon as the gate. However, he was not able to prove it to the appellate court, who sided with the Bell Labs team.

The self-aligned gate typically involves ion implantation, another semiconductor process innovation of the 1960s. The histories of ion implantation and self-aligned gates are highly interrelated, as recounted in an in-depth history by R.B. Fair. [8]

The first commercial product using self-aligned silicon-gate technology was the Fairchild 3708 8-bit analog multiplexor, in 1968, designed by Federico Faggin who pioneered several inventions in order to turn the aforementioned non working proofs of concept, into what the industry actually adopted thereafter. [9] [10]

Manufacturing process

The importance of self-aligned gates comes in the process used to make them. The process of using the gate oxide as a mask for the source and drain diffusion both simplifies the process and greatly improves the yield.

Process steps

The following are the steps in creating a self-aligned gate: [11]

A cleanroom facility where these steps are performed Cleanroom1.jpg
A cleanroom facility where these steps are performed

These steps were first created by Federico Faggin and used in the Silicon Gate Technology process developed at Fairchild Semiconductor in 1968 for the fabrication of the first commercial integrated circuit using it, the Fairchild 3708 [12]

1. Wells on the field oxide are etched where the transistors are to be formed. Each well defines the source, drain, and active gate regions of an MOS transistor.
2. Using a dry thermal oxidation process, a thin layer (5-200 nm) of gate oxide (SiO2) is grown on the silicon wafer.
3. Using a chemical vapor deposition (CVD) process, a layer of polysilicon is grown on top of the gate oxide.
4. A layer of photoresist is applied on top of the polysilicon.
5. A mask is placed on top of the photoresist and exposed to UV light; this breaks down the photoresist layer in areas where the mask didn't protect it.
6. Photoresist is exposed with a specialized developer solution. This is intended to remove the photoresist that was broken down by the UV light.
7. The polysilicon and gate oxide that is not covered by photoresist is etched away with a buffered ion etch process. This is usually an acid solution containing hydrofluoric acid.
8. The rest of the photoresist is stripped from the silicon wafer. There is now a wafer with polysilicon over the gate oxide, and over the field oxide.
9. The thin oxide is etched away exposing the source and drain regions of the transistor, except in the gate region which is protected by the polysilicon gate.
10. Using a conventional doping process, or a process called ion-implantation, the source, drain and the polysilicon are doped. The thin oxide under the silicon gate acts as a mask for the doping process. This step is what makes the gate self-aligning. The source and drain regions are automatically properly aligned with the (already in place) gate.
11. The wafer is annealed in a high temperature furnace (>800 °C or 1,500 °F). This diffuses the dopant further into the crystal structure to make the source and drain regions and results in the dopant diffusing slightly underneath the gate.
12. The process continues with vapor deposition of silicon dioxide to protect the exposed areas, and with all the remaining steps to complete the process.

See also

Related Research Articles

N-type metal-oxide-semiconductor logic uses n-type MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off, triode, saturation, and velocity saturation.

CMOS Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuits (ICs), including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

Federico Faggin Italian physicist and electrical engineer

Federico Faggin is an Italian-American physicist, engineer, inventor and entrepreneur. He is best known for designing the first commercial microprocessor, the Intel 4004. He led the 4004 (MCS-4) project and the design group during the first five years of Intel's microprocessor effort. Faggin also created, while working at Fairchild Semiconductor in 1968, the self-aligned MOS (metal-oxide-semiconductor) silicon-gate technology (SGT), which made possible MOS semiconductor memory chips, CCD image sensors, and the microprocessor. After the 4004, he led development of the Intel 8008 and 8080, using his SGT methodology for random logic chip design, which was essential to the creation of early Intel microprocessors. He was co-founder and CEO of Zilog, the first company solely dedicated to microprocessors, and led the development of the Zilog Z80 and Z8 processors. He was later the co-founder and CEO of Cygnet Technologies, and then Synaptics.

Threshold voltage Minimum source-to-gate voltage for a field effect transistor to be conducting from source to drain

The threshold voltage, commonly abbreviated as Vth, of a field-effect transistor (FET) is the minimum gate-to-source voltage VGS (th) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.

Power MOSFET power MOS field-effect transistor

A power MOSFET is a specific type of MOSFET designed to handle significant power levels.

Depletion-load NMOS logic form of nMOS logic family

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier nMOS logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

Capacitance–voltage profiling is a technique for characterizing semiconductor materials and devices. The applied voltage is varied, and the capacitance is measured and plotted as a function of voltage. The technique uses a metal–semiconductor junction or a p–n junction or a MOSFET to create a depletion region, a region which is empty of conducting electrons and holes, but may contain ionized donors and electrically active defects or traps. The depletion region with its ionized charges inside behaves like a capacitor. By varying the voltage applied to the junction it is possible to vary the depletion width. The dependence of the depletion width upon the applied voltage provides information on the semiconductor's internal characteristics, such as its doping profile and electrically active defect densities., Measurements may be done at DC, or using both DC and a small-signal AC signal, or using a large-signal transient voltage.

The floating-gate MOSFET (FGMOS) is a type of MOSFET where the gate is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify the amount of charge stored in the FG.

Charge trap flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. The technology differs from the more conventional floating-gate MOSFET technology in that it uses a silicon nitride film to store electrons rather than the doped polycrystalline silicon typical of a floating gate structure. This approach allows memory manufacturers to reduce manufacturing costs five ways:

  1. Fewer process steps are required to form a charge storage node
  2. Smaller process geometries can be used
  3. Multiple bits can be stored on a single flash memory cell.
  4. Improved reliability
  5. Higher yield since the charge trap is less susceptible to point defects in the tunnel oxide layer

Hot carrier injection (HCI) is a phenomenon in solid-state electronic devices where an electron or a “hole” gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The term "hot" refers to the effective temperature used to model carrier density, not to the overall temperature of the device. Since the charge carriers can become trapped in the gate dielectric of a MOS transistor, the switching characteristics of the transistor can be permanently changed. Hot-carrier injection is one of the mechanisms that adversely affects the reliability of semiconductors of solid-state devices.

SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"siicon dioxide"—"silicon", is a cross sectional structure of MOSFET, realized by P.C.Y. Chen in 1977. This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays. It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material. A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon"). Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia.

PMOS logic p-type MOSFETs to implement logic gates

P-type metal-oxide-semiconductor logic uses p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-type transistor body. This inversion layer, called the p-channel, can conduct holes between p-type "source" and "drain" terminals.

The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET from the underlying source and drain terminals as well as the conductive channel that connects source and drain when the transistor is turned on. Gate oxide is formed by thermal oxidation of the silicon of the channel to form a thin insulating layer of silicon dioxide. The insulating silicon dioxide layer is formed through a process of self-limiting oxidation, which is described by the Deal Grove model. A conductive gate material is subsequently deposited over the gate oxide to form the transistor. The gate oxide serves as the dielectric layer so that the gate can sustain as high as 1 to 5 MV/cm transverse electric field in order to strongly modulate the conductance of the channel.

Robert W. Bower is an American applied physicist. Immediately after receiving his Ph.D. from The California Institute of Technology in 1973, he worked for over 25 years in many different professions: Engineer, Scientist, Department Head at University of California, Davis, and as president and CEO of Device Concept Inc. He also served as the President of Integrated Vertical Modules, which focused on three-dimensional, high-density structures. His most notable contribution, however, is his field-effect device with insulated gates—also known as a self-aligned-gate MOSFET, or SAGFET. Bower patented this design in 1969 while working at the Hughes Research Laboratories in Malibu, California. He has also published over 80 journals and articles, patented over 28 inventions, and authored chapters in 3 different books.

In electronics, a native transistor is a variety of the MOS field-effect transistor that is intermediate between enhancement and depletion modes. Most common is the n-channel native transistor.

Polysilicon depletion effect is the phenomenon in which unwanted variation of threshold voltage of the MOSFET devices using polysilicon as gate material is observed, leading to unpredicted behavior of the electronic circuit. Polycrystalline silicon, also called polysilicon, is a material consisting of small silicon crystals. It differs from single-crystal silicon, used for electronics and solar cells, and from amorphous silicon, used for thin film devices and solar cells.

Field-effect transistor transistor that uses an electric field to control the electrical behaviour of the device. FETs are also known as unipolar transistors since they involve single-carrier-type operation

The field-effect transistor (FET) is an electronic device which uses an electric field to control the flow of current. FETs are devices with three terminals: source, gate, and drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source.


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