Silicon on insulator

Last updated

In semiconductor manufacturing, Silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. [1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. [2] The insulating layer and topmost silicon layer also vary widely with application. [3]

Silicon Chemical element with atomic number 14

Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard and brittle crystalline solid with a blue-grey metallic lustre; and it is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic table: carbon is above it; and germanium, tin, and lead are below it. It is relatively unreactive. Because of its high chemical affinity for oxygen, it was not until 1823 that Jöns Jakob Berzelius was first able to prepare it and characterize it in pure form. Its melting and boiling points of 1414 °C and 3265 °C respectively are the second-highest among all the metalloids and nonmetals, being only surpassed by boron. Silicon is the eighth most common element in the universe by mass, but very rarely occurs as the pure element in the Earth's crust. It is most widely distributed in dusts, sands, planetoids, and planets as various forms of silicon dioxide (silica) or silicates. More than 90% of the Earth's crust is composed of silicate minerals, making silicon the second most abundant element in the Earth's crust after oxygen.

Substrate is a term used in materials science to describe the base material on which processing is conducted to produce new film or layers of material such as deposited coatings.

Parasitic capacitance, or stray capacitance is an unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. When two electrical conductors at different voltages are close together, the electric field between them causes electric charge to be stored on them; this effect is parasitic capacitance. All actual circuit elements such as inductors, diodes, and transistors have internal capacitance, which can cause their behavior to depart from that of 'ideal' circuit elements. Additionally, there is always non-zero capacitance between any two conductors; this can be significant at higher frequencies with closely spaced conductors, such as wires or printed circuit board traces. Parasitic capacitance is a significant problem in high frequency circuits and is often the factor limiting the operating frequency and bandwidth of electronic components and circuits.

Contents

Industry need

SOI technology is one of several manufacturing strategies to allow the continued miniaturization of microelectronic devices, colloquially referred to as "extending Moore's Law" (or "More Moore", abbreviated "MM"). Reported benefits of SOI relative to conventional silicon (bulk CMOS) processing include: [4]

CMOS Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuits (ICs), including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

IC power-supply pin

Almost all integrated circuits (ICs) have at least two pins that connect to the power rails of the circuit in which they are installed. These are known as the power-supply pins. However, the labeling of the pins varies by IC family and manufacturer.

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 1015% increase to total manufacturing costs. [6] [ additional citation(s) needed ]

Metrology Science of measurement and its application

Metrology is the science of measurement. It establishes a common understanding of units, crucial in linking human activities. Modern metrology has its roots in the French Revolution's political motivation to standardise units in France, when a length standard taken from a natural source was proposed. This led to the creation of the decimal-based metric system in 1795, establishing a set of standards for other types of measurements. Several other countries adopted the metric system between 1795 and 1875; to ensure conformity between the countries, the Bureau International des Poids et Mesures (BIPM) was established by the Metre Convention. This has evolved into the International System of Units (SI) as a result of a resolution at the 11th Conference Generale des Poids et Mesures (CGPM) in 1960.

SOI transistors

An SOI MOSFET is a semiconductor device (MOSFET) in which a semiconductor layer such as silicon or germanium is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate. [7] [8] [9] SOI MOSFET devices are adapted for use by the computer industry.[ citation needed ] The buried oxide layer can be used in SRAM designs. [10] There are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX) supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation. [11] [12] Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film is not connected to any of the supplies.[ citation needed ]

A semiconductor material has an electrical conductivity value falling between that of a conductor, such as metallic copper, and an insulator, such as glass. Its resistance decreases as its temperature increases, which is the behaviour opposite to that of a metal. Its conducting properties may be altered in useful ways by the deliberate, controlled introduction of impurities ("doping") into the crystal structure. Where two differently-doped regions exist in the same crystal, a semiconductor junction is created. The behavior of charge carriers which include electrons, ions and electron holes at these junctions is the basis of diodes, transistors and all modern electronics. Some examples of semiconductors are silicon, germanium, gallium arsenide, and elements near the so-called "metalloid staircase" on the periodic table. After silicon, gallium arsenide is the second most common semiconductor and is used in laser diodes, solar cells, microwave-frequency integrated circuits and others. Silicon is a critical element for fabricating most electronic circuits.

MOSFET Transistor used for amplifying or switching electronic signals.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of field-effect transistor that is fabricated by the controlled oxidation of a semiconductor, typically silicon. It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET is the basic building block of modern electronics. Since its invention by Mohamed M. Atalla and Dawon Kahng at Bell Labs in November 1959, the MOSFET has become the most widely manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOS transistors manufactured between 1960 and 2018.

Germanium Chemical element with atomic number 32

Germanium is a chemical element with the symbol Ge and atomic number 32. It is a lustrous, hard-brittle, grayish-white metalloid in the carbon group, chemically similar to its group neighbours silicon and tin. Pure germanium is a semiconductor with an appearance similar to elemental silicon. Like silicon, germanium naturally reacts and forms complexes with oxygen in nature.

Manufacture of SOI wafers

SIMOX process SIMOX processing schematic.svg
SIMOX process
Smart Cut process Smart Cut SOI Wafer Manufacturing Schema.svg
Smart Cut process

SiO2-based SOI wafers can be produced by several methods:

Ion implantation Material and chemical process

Ion implantation is a low-temperature process by which ions of one element are accelerated into a solid target, thereby changing the physical, chemical, or electrical properties of the target. Ion implantation is used in semiconductor device fabrication and in metal finishing, as well as in materials science research. The ions can alter the elemental composition of the target if they stop and remain in the target. Ion implantation also causes chemical and physical changes when the ions impinge on the target at high energy. The crystal structure of the target can be damaged or even destroyed by the energetic collision cascades, and ions of sufficiently high energy can cause nuclear transmutation.

Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically sealed encapsulation. The wafers' diameter range from 100 mm to 200 mm for MEMS/NEMS and up to 300 mm for the production of microelectronic devices. Smaller wafers were used in the early days of the microelectronics industry, with wafers being just 1 inch in diameter in the 1950s.

Soitec is a France-based international industrial company specialized in generating and manufacturing high performance semiconductor materials.

An exhaustive review of these various manufacturing processes may be found in reference [1]

Microelectronics industry

Research

The silicon-on-insulator concept dates back to 1964, when it was proposed by C.W. Miller and P.H. Robinson. [20] In 1979, a Texas Instruments research team including A.F. Tasch, T.C. Holloway and Kai Fong Lee fabricated a silicon-on-insulator MOSFET (metal-oxide-semiconductor field-effect transistor). [21] In 1983, a Fujitsu research team led by S. Kawamura fabricated a three-dimensional integrated circuit with SOI CMOS (complementary metal-oxide-semiconductor) structure. [22] In 1984, the same Fujitsu research team fabricated a 3D gate array with vertically-stacked dual SOI/CMOS structure using beam recrystallization. [23] The same year, Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi fabricated a double-gate MOSFET, demonstrating that short-channel effects can be significantly reduced by sandwiching a fully depleted SOI device between two gate electrodes connected together. [24] [25]

In 1989, Ghavam Shahidi initiated the SOI Research Program at the IBM Thomas J Watson Research Center. [26] He was the chief architect of SOI technology at IBM Microelectronics, where he made fundamental contributions, from materials research to the development of the first commercially viable devices, with the support of his boss Bijan Davari. [27] Shahidi was a key figure in making SOI CMOS technology a manufacturable reality. In the early 1990s, he demonstrated a novel technique of combining silicon epitaxial overgrowth and chemical mechanical polishing to prepare device-quality SOI material for fabricating devices and simple circuits, which led to IBM expanding its research program to include SOI substrates. He was also the first to demonstrate the power-delay advantage of SOI CMOS technology over traditional bulk CMOS in microprocessor applications. He overcame barriers preventing the semiconductor industry's adoption of SOI, and was instrumental in driving SOI substrate development to the quality and cost levels suitable for mass-production. [28]

In 1998, a team of Hitachi, TSMC and UC Berkeley researchers demonstrated the FinFET (fin field-effect transistor), [29] which is a non-planar, double-gate MOSFET built on an SOI substrate. [30] In early 2001, Shahidi used SOI to developed a low-power RF CMOS device, resulting in increased radio frequency, at IBM. [27]

Commercialization

Ghavam Shahidi's research at IBM led to the first commercial use of SOI in mainstream CMOS technology. [26] SOI was first commercialized in 1995, when Shahidi's work on SOI convinced John Kelly, who ran IBM's server division, to adopt SOI in the AS/400 line of server products, which used 220 nm CMOS with copper metallization SOI devices. [27] IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001. [31]

In late 2001, IBM was set to introduce 130 nanometer CMOS SOI devices with copper and low-κ dielectric for the back end, based on Shahidi's work. [27] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001. Currently,[ when? ] Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines. [32] The 90 nm PowerPC- and Power ISA-based processors used in the Xbox 360, PlayStation 3, and Wii use SOI technology as well. Competitive offerings from Intel however continue[ when? ] to use conventional bulk CMOS technology for each process node, instead focusing on other venues such as HKMG and tri-gate transistors to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI. [33]

As for the traditional foundries, on July 2006 TSMC claimed no customer wanted SOI, [34] but Chartered Semiconductor devoted a whole fab to SOI. [35]

Use in high-performance radio frequency (RF) applications

In 1990, Peregrine Semiconductor began development of an SOI process technology utilizing a standard 0.5 μm CMOS node and an enhanced sapphire substrate. Its patented silicon on sapphire (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios. [36] [ additional citation(s) needed ]

Use in photonics

SOI wafers are widely used in silicon photonics. [37] The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications), or covered with a cladding, typically made of silica.[ citation needed ]

See also

Related Research Articles

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny MOS transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Semiconductor device fabrication manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, particularly the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Thin-film transistor field-effect transistor device

A thin-film transistor (TFT) is a special kind of MOSFET made by depositing thin films of an active semiconductor layer as well as the dielectric layer and metallic contacts over a supporting substrate. A common substrate is glass, because the primary application of TFTs is in liquid-crystal displays (LCDs). This differs from the conventional bulk MOSFET transistor, where the semiconductor material typically is the substrate, such as a silicon wafer.

SiGe, or silicon-germanium, is an alloy with any molar ratio of silicon and germanium, i.e. with a molecular formula of the form Si1−xGex. It is commonly used as a semiconductor material in integrated circuits (ICs) for heterojunction bipolar transistors or as a strain-inducing layer for CMOS transistors. IBM introduced the technology into mainstream manufacturing in 1989. This relatively new technology offers opportunities in mixed-signal circuit and analog circuit IC design and manufacture. SiGe is also used as a thermoelectric material for high temperature applications.

A MESFET is a field-effect transistor semiconductor device similar to a JFET with a Schottky (metal-semiconductor) junction instead of a p-n junction for a gate.

The 90 nanometer (90 nm) process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

Threshold voltage Minimum source-to-gate voltage for a field effect transistor to be conducting from source to drain

The threshold voltage, commonly abbreviated as Vth, of a field-effect transistor (FET) is the minimum gate-to-source voltage VGS (th) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.

FinFET semiconductor manufacturing process

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS technology.

The 22 nanometer (22 nm) node is the process step following the 32 nm in MOSFET (CMOS) semiconductor device fabrication. The typical half-pitch for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012.

The 130 nanometer (130 nm) process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 2001-2002 timeframe, by leading semiconductor companies like Fujitsu, IBM, Intel, Texas Instruments, and TSMC.

Multigate device type of MOS field-effect transistor with more than one gate

A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a MOSFET that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are the FinFET and the GAAFET, which are non-planar transistors, or 3D transistors.

Ghavam G. Shahidi is an Iranian-American electrical engineer and IBM Fellow. He is the director of Silicon Technology at the IBM Thomas J Watson Research Center. He is best known for his pioneering work in silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) technology since the late 1980s.

Nanocircuits are electrical circuits operating on the nanometer scale. This is well into the quantum realm, where quantum mechanical effects become very important. One nanometer is equal to 10−9 meters or a row of 10 hydrogen atoms. With such progressively smaller circuits, more can be fitted on a computer chip. This allows faster and more complex functions using less power. Nanocircuits are composed of three different fundamental components. These are transistors, interconnections, and architecture, all fabricated on the nanometer scale.

The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET from the underlying source and drain terminals as well as the conductive channel that connects source and drain when the transistor is turned on. Gate oxide is formed by thermal oxidation of the silicon of the channel to form a thin insulating layer of silicon dioxide. The insulating silicon dioxide layer is formed through a process of self-limiting oxidation, which is described by the Deal Grove model. A conductive gate material is subsequently deposited over the gate oxide to form the transistor. The gate oxide serves as the dielectric layer so that the gate can sustain as high as 1 to 5 MV/cm transverse electric field in order to strongly modulate the conductance of the channel.

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nanometer (5 nm) node as the MOSFET technology node following the 7 nm node. As of 2019, Samsung Electronics and TSMC have begun commercial production of 5 nm nodes.

Field-effect transistor transistor that uses an electric field to control the electrical behaviour of the device. FETs are also known as unipolar transistors since they involve single-carrier-type operation

The field-effect transistor (FET) is an electronic device which uses an electric field to control the flow of current. FETs are devices with three terminals: source, gate, and drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source.

A ferroelectric field-effect transistor is a type of field-effect transistor that includes a ferroelectric material sandwiched between the gate electrode and source-drain conduction region of the device - permanent electrical field polarisation in the ferroelectric cause this type of device to retain the transistor's state in the absence of any electrical bias.

References

  1. 1 2 Celler, G. K.; Cristoloveanu, S. (2003). "Frontiers of silicon-on-insulator" (PDF). J Appl Phys . 93 (9): 4955. doi:10.1063/1.1558223.
  2. Marshall, Andrew; Natarajan, Sreedhar (2002). SOI design: analog, memory and digital techniques. Boston: Kluwer. ISBN   0792376404.
  3. Colinge, Jean-Pierre (1991). Silicon-on-Insulator Technology: Materials to VLSI. Berlin: Springer Verlag. ISBN   978-0-7923-9150-0.
  4. Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications by Horacio Mendez, Executive Director of the SOI Industry Consortium, April 9, 2009
  5. "Archived copy" (PDF). Archived from the original (PDF) on 2013-04-18. Retrieved 2014-04-12.CS1 maint: archived copy as title (link)
  6. "IBM touts chipmaking technology". cnet.com. 29 March 2001. Retrieved 22 April 2018.
  7. United States Patent 6,835,633 SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer
  8. United States Patent 7,002,214 Ultra-thin body super-steep retrograde well (SSRW) FET devices
  9. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era; Yang-Kyu Choi; Asano, K.; Lindert, N.; Subramanian, V.; Tsu-Jae King; Bokor, J.; Chenming Hu; Electron Device Letters, IEEE; Volume 21, Issue 5, May 2000 Page(s):254 - 255
  10. United States Patent 7138685 " Vertical MOSFET SRAM cell" describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures.
  11. F. Balestra, Characterization and Simulation of SOI MOSFETs with Back Potential Control, PhD thesis, INP-Grenoble, 1985
  12. F. Balestra, Challenges to Ultralow-Power Semiconductor Device Operation, in "Future Trends in Microelectronics-Journey into the unknown", S. Lury, J. Xu, A. Zaslavsky Eds., J. Wiley & Sons, 2016
  13. U.S. Patent 5,888,297 Method of fabricating SOI substrate Atsushi Ogura, Issue date: Mar 30, 1999
  14. U.S. Patent 5,061,642 Method of manufacturing semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991
  15. "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, ISBN   978-0-471-57481-1
  16. U.S. Patent 4,771,016 Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988
  17. "SIGEN.COM". www.sigen.com. Retrieved 22 April 2018.
  18. ELTRAN - Novel SOI Wafer Technology Archived 2007-09-27 at the Wayback Machine , JSAPI vol.4
  19. U.S. Patent 5,417,180
  20. Colinge, J.P. (2003). "Multiplate-Gate Silicon-On-Insulator MOS Transistors". Microelectronics Technology and Devices, SBMICRO 2003: Proceedings of the Eighteenth International Symposium. The Electrochemical Society. pp. 2–17. ISBN   9781566773898.
  21. Tasch, A. F.; Holloway, T. C.; Lee, K. F.; Gibbons, J. F. (1979). "Silicon-on-insulator m.o.s.f.e.t.s fabricated on laser-annealed polysilicon on SiO2". Electronics Letters. 15 (14): 435–437. doi:10.1049/el:19790312.
  22. Kawamura, S.; Sasaki, N.; Iwai, T.; Mukai, R.; Nakano, M.; Takagi, M. (December 1983). "3-Dimensional SOI/CMOS IC's fabricated by beam recrystallization". 1983 International Electron Devices Meeting: 364–367. doi:10.1109/IEDM.1983.190517.
  23. Kawamura, S.; Sasaki, Nobuo; Iwai, T.; Mukai, R.; Nakano, M.; Takagi, M. (1984). "3-Dimensional Gate Array with Vertically Stacked Dual SOI/CMOS Structure Fabricated by Beam Recrystallization". 1984 Symposium on VLSI Technology. Digest of Technical Papers: 44–45.
  24. Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 11. ISBN   9780387717517.
  25. Sekigawa, Toshihiro; Hayashi, Yutaka (1 August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. doi:10.1016/0038-1101(84)90036-4. ISSN   0038-1101.
  26. 1 2 "Ghavam G. Shahidi". IEEE Xplore . Institute of Electrical and Electronics Engineers . Retrieved 16 September 2019.
  27. 1 2 3 4 "SOI scientist counted among latest IBM fellows". EE Times . 30 May 2001.
  28. "Ghavam Shahidi". Engineering and Technology History. Institute of Electrical and Electronics Engineers . Retrieved 16 September 2019.
  29. Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley . Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.
  30. Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, C.; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. doi:10.1109/16.918235.
  31. Vries, Hans de. "Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed". chip-architect.com. Retrieved 22 April 2018.
  32. "NXP Semiconductors - Automotive, Security, IoT". www.freescale.com. Retrieved 22 April 2018.
  33. Rong, Haisheng; Liu, Ansheng; Jones, Richard; Cohen, Oded; Hak, Dani, Nicolaescu, Remus; Fang, Alexander; Paniccia, Mario (January 2005). "An all-silicon Raman laser" (PDF). Nature. 433: 292–294. doi:10.1038/nature03723.CS1 maint: uses authors parameter (link)
  34. "TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals". fabtech.org. Archived from the original on 28 September 2007. Retrieved 22 April 2018.
  35. Chartered expands foundry market access to IBM's 90nm SOI technology
  36. Madden, Joe. "Handset RFFEs: MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO" (PDF). Mobile Experts. Archived from the original (PDF) on 4 March 2016. Retrieved 2 May 2012.
  37. Reed, Graham T.; Knights, Andrew P. (5 March 2004). "Silicon Photonics: An Introduction". Wiley. Retrieved 22 April 2018 via Google Books.