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A Small Outline Integrated Circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. The convention for naming the package is SOIC or SO followed by the number of pins. For example, a 14-pin 4011 would be housed in an SOIC-14 or SO-14 package.
Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBs). An electronic device so made is called a surface-mount device (SMD). In industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board, with the through-hole technology used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.
An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny transistors into a small chip results in circuits that are orders of magnitude smaller, cheaper, and faster than those constructed of discrete electronic components. The IC's mass production capability, reliability and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.
In microelectronics, a dual in-line package, or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits. Increasingly complex circuits required more signal and power supply leads ; eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density packages. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.
SOIC actually refers to at least two different package standards: The EIAJ SOIC body is approximately 5.3 mm (0.21 in) wide, while the JEDEC SOIC body is approximately 3.8 mm (0.15 in) wide. The EIAJ packages are also thicker and slightly longer. Otherwise the packages are similar.
Founded in 1948, the Electronic Industries Association of Japan (EIAJ) was one of two Japanese electronics trade organizations that were merged into the Japan Electronics and Information Technology Industries Association (JEITA).
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body.
Note that because of this, SOIC is not specific enough of a term to describe parts which are interchangeable. Many electronic retailers will list parts in either package as SOIC whether they are referring to the JEDEC or EIAJ standards. The wider EIAJ packages are more common with higher pin count ICs, but there is no guarantee that an SOIC package with any number of pins will be either one or the other.
The SOIC package is shorter and narrower than DIPs, the side-to-side pitch being 6 mm for an SOIC-14 (from lead tip to lead tip) and the body width being 3.9 mm. These dimensions differ depending on the SOIC in question, and there are several variants. This package has "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 in (1.27 mm).
The picture below shows the general shape of a SOIC narrow package, with major dimensions. The values of these dimensions (in mm) for common SOICs is shown in the table.
C Clearance between IC body and PCB H Total carrier height T Lead thickness L Total carrier length LW Lead width LL Lead length P Pitch WB IC body width WL Lead-to-lead width O End overhang
|SOIC-8||5.41 (5.16)||8.07 (7.67)|
Next to the narrow SOIC package (commonly represented as SOx_N or SOICx_N, where x is the number of pins), there's also the wide (or sometimes called extended) version. This package is commonly represented as SOx_W or SOICx_W.
The difference is mainly related to the parameters WB and WL. As an example, the values WB and WL are given for an 8-pins wide (extended) SOIC package.
Another SOIC variant, available only for 8-pins and 10-pins ICs, is the mini-SOIC, also called micro-SOIC. This case is much smaller with a pitch of only 0.5 mm. See the following table for the 10-pin model:
An excellent overview of different semiconductor packages can be found here.
Small-outline J-leaded package (SOJ) is a version of SOIC with J-type leads instead of gull-wing leads.
After SOIC came a family of smaller form factors, small-outline package (SOP), with pin spacings less than 1.27 mm:
Shrink small-outline package (SSOP) chips have "gull wing" leads protruding from the two long sides, and a lead spacing of 0.0256 inches (0.65 mm) or 0.025 inches (0.635 mm) . 0.5 mm lead spacing is less common, but not rare.
The body size of a SOP was compressed and the lead pitch tightened to obtain a smaller version SOP. This yields an IC package which is a significant reduction in the size (compared to standard package). All IC assembly processes remain the same as with standard SOPs.
Applications for a SSOP enable end-products (pagers, portable audio/video, disc drives, radio, RF devices/components, telecom) to be reduced in size and weight. Semiconductor families such as operational amplifiers, drivers, optoelectronics, controllers, logic, analog, memory, comparators and more using BiCMOS, CMOS or other silicon / GaAs technologies are well addressed by the SSOP product family.
A thin small-outline package (TSOP) is a rectangular, thin bodied component. The ICs on DRAM memory modules were usually TSOPs until they were replaced by ball grid array (BGA).
Thin Small Outline Package, or TSOP is a type of surface mount IC package. They are very low-profile and have tight lead spacing.
A DIMM or dual in-line memory module comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs as the predominant type of memory module as Intel P5-based Pentium processors began to gain market share.
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.
A thin-shrink small-outline package (TSSOP) is a rectangular, thin body size component. A Type I TSSOP has legs protruding from the width portion of the package. A Type II TSSOP has the legs protruding from the length portion of the package. A TSSOP's leg count can range from 8 to 64.
TSSOPs are particularly suited for gate drivers, controllers, wireless / RF, op-amps, logic, analog, ASICs, memory (EPROM, E2PROM), comparators and optoelectronics. Memory modules, disk drives, recordable optical disks, telephone handsets, speed dialers, video / audio and consumer electronics / appliances are suggested uses for TSSOP packaging.
The Exposed Pad (EP) variant of small outline packages can increase heat dissipation by as much as 1.5 times over a standard TSSOP, thereby expanding the margin of operating parameters. Additionally, the Exposed Pad can be connected to ground, thereby reducing loop inductance for high frequency applications. The ExposedPad should be soldered directly to the PCB to realize the thermal and electrical benefits.
The zig-zag in-line package or ZIP is a packaging technology for integrated circuits. It was intended as a replacement for dual in-line packaging. A ZIP is an integrated circuit encapsulated in a slab of plastic with 20 or 40 pins, measuring about 3 mm x 30 mm x 10 mm. The package's pins protrude in two rows from one of the long edges. The two rows are staggered by 1.27 mm (0.05"), giving them a zig-zag appearance, and allowing them to be spaced more closely than a rectangular grid would allow. The pins are inserted into holes in a printed circuit board, with the packages standing at right-angles to the board, allowing them to be placed closer together than DIPs of the same size. ZIPs have now been superseded by surface-mount packages such as the thin small-outline packages (TSOPs) but they are still in use.
In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.
A QFP or Quad Flat Package is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP).
In electronics, a lead is an electrical connection consisting of a length of wire or a metal pad (SMD) that is designed to connect two locations electrically. Leads are used for many purposes, including: transfer of power; testing of an electrical circuit to see if it is working, using a test light or a multimeter; transmiting information, as when the leads from an electrocardiograph, or ECG are attached to a person's body to transmit information about their heart rhythm; and sometimes to act as a heatsink. The tiny leads coming off through-hole components are also often called pins.
The TO-92 is a widely used style of semiconductor package mainly used for transistors. The case is often made of epoxy or plastic, and offers compact size at a very low cost.
Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).
In electronics, TO-3 is a designation for a standardized metal semiconductor package used for power semiconductors, including transistors, silicon controlled rectifiers, and, integrated circuits. TO stands for "Transistor Outline" and relates to a series of technical drawings produced by JEDEC.
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.
In microelectronics, a three-dimensional integrated circuit is an integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. 3D IC is just one of a host of 3D integration schemes that exploit the z-direction to achieve electrical performance benefits.
Non contact wafer testing is a normal step in semiconductor device fabrication, used to detect defects in integrated circuits (IC) before they are assembled during the IC packaging step.
In electronics, TO-18 is a designation for a style of transistor metal case. The case is more expensive than the similarly sized plastic TO-92 package. The name is from JEDEC, signifying Transistor Outline Package, Case Style 18.
Quadracs are a special type of thyristor which combines a "diac" and a "triac" in a single package. The diac is the triggering device for the triac. Thyristors are four-layer (PNPN) semiconductor devices that act as switches, rectifiers or voltage regulators in a variety of applications. When triggered, thyristors turn on and become low-resistance current paths. They remain so even after the trigger is removed, and until the current is reduced to a certain level. Diacs are bi-directional diodes that switch AC voltages and trigger triacs or silicon-controlled rectifiers (SCRs). Except for a small leakage current, diacs do not conduct until the breakover voltage is reached. Triacs are three-terminal, silicon devices that function as two SCRs configured in an inverse, parallel arrangement. They provide load current during both halves of the AC supply voltage. By combining the functions of diacs and triacs, quadracs eliminate the need to buy and assemble discrete parts.
In electronics, a chip carrier is one of several kinds of surface-mount technology packages for integrated circuits. Connections are made on all four edges of a square package; Compared to the internal cavity for mounting the integrated circuit, the package overall size is large.
A small outline transistor (SOT) is a family of small footprint, discrete surface mount transistor commonly used in consumer electronics. The most common SOT are SOT23 variations, also manufacturers offer the nearly identical thin small outline transistor (TSOT) package, where lower height is important.