Three-state bus

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A three-state bus is a computer bus connected to multiple tri-state output devices, only one of which can be enabled at any point to avoid bus contention. This scheme allows for the same bus to be shared among multiple devices.

Bus contention, in computer design, is an undesirable state of the bus in which more than one device on the bus attempts to place values on the bus at the same time. Most bus architectures require their devices to follow an arbitration protocol carefully designed to make the likelihood of contention negligible. However, when devices on the bus have logic errors, manufacturing defects, or are driven beyond their design speeds, arbitration may break down and contention may result. Contention may also arise on systems which have a programmable memory mapping when illegal values are written to the registers controlling the mapping.

Each three-state bus usually has associated control signals from a decoder that select one device at a time to drive data onto the three-state bus.

In digital electronics, a binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2n unique outputs. They are used in a wide variety of applications, including data demultiplexing, seven segment displays, and memory address decoding.

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