Tick–tock model

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Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick–tock is a model that refreshes one side of a binary system each release cycle.

Contents

History

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (sometimes introducing new instructions, as with Broadwell, released in late 2014) and every "tock" designated a new microarchitecture. [1] These occurred roughly every year to 18 months. [2] In 2014, Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture [3] not considered a new generation in and of itself.

In March 2016, Intel announced in a Form 10-K report that it deprecated the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization. [4] The first optimization of the Skylake architecture was Kaby Lake. Intel then announced a second optimization, Coffee Lake, [5] making a total of four generations at 14 nm. [6]

Roadmap

Pentium 4 / Core roadmap

Pentium 4 / Core roadmap
Change
(step)		 Fabri­cation
process 		Micro-
architecture 		Code names
for step		Intel
Generation
Desktop		Intel
Generation
Xeon		Intel Microcode
shortcut(s)
Desktop/WS [7] [8] 		Intel Microcode
shortcut(s)
Xeon/Server		Release
date		Processors
8P/4P Server4P/2P Server/WSEmbedded Xeon1P XeonEnthusiast/WSDesktopMobile
Tick
(new fabrica-
tion process)		 65 nm P6, NetBurst Yonah (P6),
Presler (NetBurst),
Cedar Mill (NetBurst)		—1995-11-1 (P6),
2000-11-20 (Netburst)		——— Presler (NetBurst) Cedar Mill (NetBurst) Yonah (P6)
Tock
(new micro-
architecture)		 Core Merom [9] 2006-07-27 [10] [11] Tigerton Woodcrest
Clovertown 		Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11 [12] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 1—NHM [13] —2008-11-17 [14] Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 1WSM [13] 2010-01-04 [15] [16] Westmere-EX Westmere-EP — Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 21SNBJKT (Jaketown)2011-01-09 [17] (Skipped) [18] Sandy Bridge-EP GladdenSandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm [19] Ivy Bridge 32IVBIVT (Ivytown)2012-04-29Ivy Bridge-EX [20] Ivy Bridge-EP [20] GladdenIvy BridgeIvy Bridge-E [21] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 43HSW, CRW (Crystal Well)
with Iris Pro [22] [23] 		HSX2013-06-02Haswell-EXHaswell-EP—Haswell-DTHaswell-EHaswell-DT [24] Haswell-MB (notebooks)
Haswell-LP (ultrabooks) [24]
Refresh Haswell Refresh,
Devil's Canyon [25] 		4—HSW, CRW (Crystal Well)
with Iris Pro [22] [23] 		—}2014-05-11,
2014-06-02		No server version releasedDevil's CanyonNo mobile version
released
Tick (Process) 14 nm [19] Broadwell [26] 54BDWBDX2014-09-05Broadwell-EX [27] Broadwell-EP [27] Broadwell-DEBroadwell-DTBroadwell-EBroadwell-DTBroadwell-H
Broadwell-U
Broadwell-Y
Tock (Architecture) Skylake [26] Skylake [26] 65SKLSKX2015-08-05 [28] Skylake-SPSkylake-DESkylake-DT/HSkylake-X Skylake Skylake-H
Skylake-U
Skylake-Y
Optimization
(Refresh)
[4] [29] [30] [31] 		Kaby Lake [32] 76KBL—2017-01-03 [33] Only 1P server (Xeon E3) version released Kaby Lake-DT/H
cores: 4 (4/8)		Kaby Lake-X [34] Kaby Lake Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake R [35] [36] 8—KBL-R2017-08-21 [36] Only mobile version releasedKaby Lake R
Coffee Lake 8, 9 [37] E-2xxxCFL2017-10-05 [38] Cascade Lake-SP
Cooper Lake (Q2'20)		 Cascade Lake-AP Coffee Lake-DT/H
cores: 6 (12)		Skylake-X Refresh Coffee Lake-S
Coffee Lake-R 		Coffee Lake-H
Coffee Lake-U
Coffee Lake-H Refresh
Whiskey Lake,
Amber Lake [39] 		8—WHL
AML		2018-08-28 [39] Only mobile version releasedWhiskey Lake-U
Amber Lake-Y
Comet Lake [40] 10CML2019-08-21 [40] No server version released Comet Lake-W Comet Lake-S Comet Lake-H
Comet Lake-U
Architecture Cypress Cove [41] Rocket Lake [41] 11RKL2021-03-30 [42] —Rocket Lake-S—
Process 10 nm Palm Cove Cannon Lake 8CNL2018-05-16 [43] Only mobile version releasedCannon Lake-U
Architecture Sunny Cove Ice Lake [44] 103ICL2019-08-01 [45] Ice Lake-SP (1H21) [46] —Ice Lake-U
Ice Lake-Y
Optimization [31] Willow Cove Tiger Lake [31] 11—TGL2020-09-02 [47] Only mobile version releasedTiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Architecture Intel 7 Golden Cove Alder Lake 12ADL2021-11-04No server / WS version releasedAlder Lake-SAlder Lake-H
Alder Lake-P
Alder Lake-U
Sapphire Rapids [48] —4—SPR2022Sapphire Rapids-SPTBAOnly server / WS version released
OptimizationTBA Raptor Lake 13—RPL—2022No server / WS version releasedTBA
Emerald Rapids —5—EMR2023Emerald Rapids-SPTBAOnly server / WS version released
Tick Intel 4 [49] Meteor Lake [50] 14—MTL—2023No server / WS version releasedTBA
Tick Intel 3 Granite Rapids [51] —6—GNR2024Granite Rapids-SPTBAOnly server / WS version released
Tick Intel 20A Arrow Lake [52] 15—ARL—2024No server / WS version releasedTBA
TickIntel 18ALunar Lake16—LNL—TBANo server / WS version releasedTBA
Change
(step)		 Fabri­cation
process 		Micro-
architecture 		Code names
for step		Intel
Generation
Desktop		Intel
Generation
Xeon		Intel Microcode
shortcut(s)
Desktop/WS [7] [8] 		Intel Microcode
shortcut(s)
Xeon/Server		Release
date		8P/4P Server4P/2P Server/WSEmbedded Xeon1P XeonEnthusiast/WSDesktopMobile
Processors

Atom roadmap

With Silvermont Intel tried to start Tick-Tock in Atom architecture but problems with the 10 nm process did not allow to do this. In the table below instead of Tick-Tock steps Process-Architecture-Optimization are used. There is no official confirmation that Intel uses Process-Architecture-Optimization for Atom but it allows us to understand what changes happened in each generation.

Atom roadmap [53]
Change Fabri­cation
process 		Micro-
architecture
(Abbr.) [13] 		Code names
for step		Release
date		Processors/SoCs
MID, SmartphoneTabletNetbookNettopEmbeddedServerCE
Process / Architecture 45 nm Bonnell (BNL) Bonnell 2008 Silverthorne — Diamondville ———
Optimization Bonnell 2010 Lincroft Pineview Tunnel Creek
Stellarton		— Sodaville
Groveland
Process 32 nm Saltwell2011Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview)Clover Trail (Cloverview)Cedar Trail (Cedarview)— Centerton & Briarwood Berryville
Process / Architecture 22 nm Silvermont (SLM) Silvermont 2013Merrifield (Tangier) [54] & Moorefield (Anniedale) [55] & SlaytonBay Trail-T
(Valleyview)		Bay Trail-M
(Valleyview)		Bay Trail-D
(Valleyview)		Bay Trail-I
(Valleyview)		Avoton
Rangeley		Un­known
Process 14 nm [53] Airmont2014Binghamton & RivertonCherry Trail-T (Cherryview) [56] Braswell [57] Denverton
Cancelled cross.svgCancelled		Un­known
Architecture Goldmont [58]
(GLM)		 Goldmont 2016Broxton Cancelled cross.svgCancelledBroxton Cancelled cross.svgCancelled
Apollo Lake		Apollo LakeApollo LakeUn­knownDenvertonUn­known
Architecture Goldmont Plus
(GLM+, GLP)		 Goldmont Plus 2017Un­knownGemini LakeGemini LakeGemini LakeUn­knownUn­knownUn­known
Optimization Goldmont Plus 2019Un­knownGemini Lake RefreshGemini Lake RefreshGemini Lake RefreshUn­knownUn­knownUn­known
Process / Architecture 10 nm Tremont Tremont 2020Un­knownJasper LakeJasper LakeJasper LakeElkhart LakeSnow RidgeUn­known
Architecture Intel 7 Gracemont Gracemont 2021Un­knownUn­known Alder Lake (hybrid)Un­knownUn­known
Process / Architecture Intel 3 Un­knownUn­knownUn­knownUn­knownUn­knownUn­knownUn­knownUn­known Sierra Forest-AP Un­known

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL; [13] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology. [59]

Both

See also

Related Research Articles

Hyper-threading Proprietary simultaneous multithreading implementation by Intel

Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations performed on x86 microprocessors. It was introduced on Xeon server processors in February 2002 and on Pentium 4 desktop processors in November 2002. Since then, Intel has included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.

Pentium Brand of microprocessors produced by Intel

Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel. The original Pentium was released in 1993. After that, the Pentium II and Pentium III were released.

Intel Core Line of CPUs by Intel

Intel Core is a line of streamlined midrange consumer, workstation and enthusiast computer central processing units (CPUs) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn, Wolfdale and Yorkfield, some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Skylake (microarchitecture) CPU microarchitecture by Intel

Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a tock in Intel's tick–tock manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Cannon Lake, Whiskey Lake, and Comet Lake CPUs.

Cannon Lake is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture. As a die shrink, Cannon Lake is a new process in Intel's process-architecture-optimization execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set.

Broadwell (microarchitecture) Fifth model generation of Intel Processor

Broadwell is the fifth generation of the Intel Core Processor. It is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell.

LGA 1151 Intel microprocessor compatible socket

LGA 1151, also known as Socket H4, is an Intel microprocessor compatible socket which comes in two distinct versions: the first revision which supports both Intel's Skylake and Kaby Lake CPUs, and the second revision which supports Coffee Lake CPUs exclusively.

Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's previous "tick–tock" manufacturing and design model, Kaby Lake represents the optimized step of the newer process–architecture–optimization model. Kaby Lake began shipping to manufacturers and OEMs in the second quarter of 2016, and mobile chips have started shipping while Kaby Lake (desktop) chips were officially launched in January 2017.

Ice Lake is Intel's codename for the 10th generation Intel Core mobile and 3rd generation Xeon Scalable server processors based on the Sunny Cove microarchitecture. Ice Lake represents an Architecture step in Intel's Process-Architecture-Optimization model. Produced on the second generation of Intel's 10 nm process, 10 nm+, Ice Lake is Intel's second microarchitecture to be manufactured on the 10 nm process, following the limited launch of Cannon Lake in 2018. However, Intel altered their naming scheme in 2020 for the 10 nm process. In this new naming scheme, Ice Lake's manufacturing process is called simply 10 nm, without any appended pluses.

Coffee Lake Eighth-generation Intel Core microprocessor family

Coffee Lake is Intel's codename for its eighth generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Coffee Lake processors introduced i5 and i7 CPUs featuring six cores and Core i3 CPUs with four cores and no hyperthreading.

Sapphire Rapids is a codename for Intel's fourth generation Xeon server processors based on Intel 7, which is a rebranded 10 nm Enhanced SuperFin process. Sapphire Rapids CPUs are designed for data centers; the roughly contemporary Alder Lake is intended for the wider public.

Cascade Lake is an Intel codename for a 14 nm server, workstation and enthusiast processor microarchitecture, launched in April 2019. In Intel's Process-Architecture-Optimization model, Cascade Lake is an optimization of Skylake. Intel states that this will be their first microarchitecture to support 3D XPoint-based memory modules. It also features Deep Learning Boost instructions and mitigations for Meltdown and Spectre. Intel officially launched new Xeon Scalable SKUs on February 24, 2020.

Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.

Comet Lake is Intel's codename for its 10th generation Core microprocessors. They are manufactured using Intel's third 14 nm Skylake process refinement, succeeding the Whiskey Lake U-series mobile processor and Coffee Lake desktop processor families. Intel announced low-power mobile Comet Lake-U CPUs on August 21, 2019, H-series mobile CPUs on April 2, 2020, desktop Comet Lake-S CPUs April 30, 2020, and Xeon W-1200 series workstation CPUs on May 13, 2020. Comet Lake processors and Ice Lake 10 nm processors are together branded as the Intel "10th Generation Core" family. Intel officially launched Comet Lake-Refresh CPUs on the same day as 11th Gen Core Rocket Lake launch. The low-power mobile Comet Lake-U Core and Celeron 5205U CPUs were discontinued on July 7, 2021.

Sunny Cove is a codename for a CPU microarchitecture developed by Intel, first released in September 2019. It succeeds the Palm Cove microarchitecture and is fabricated using Intel's 10 nm process node. The microarchitecture is implemented in 10th-generation Intel Core processors for mobile and third generation Xeon scalable server processors. 10th-generation Intel Core mobile processors were released in September 2019, while the Xeon server processors were released in April 6, 2021.

Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November of 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's 7 nm class process node called Intel 7, previously referred to as 10 nm Enhanced SuperFin (10ESF).

Emerald Rapids is a codename for Intel's fifth generation Xeon server processors based on Intel 7. Emerald Rapids CPUs are designed for data centers; the roughly contemporary Raptor Lake is intended for the wider public.

Sierra Forest is a codename for Intel's first generation E-core based Xeon server processors. It is fabricated using Intel's Intel 3 process. Sierra Forest will be used as part of the Birch Stream server platform in 2024.

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