Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every new process technology was first used to manufacture a die shrink of a proven microarchitecture (tick), followed by a new microarchitecture on the now-proven process (tock). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. More generally, tick–tock is an engineering model which refreshes one half of a binary system each release cycle.
Every "tick" represented a shrinking of the process technology of the previous microarchitecture (with minor changes, commonly to the caches, and rarely introducing new instructions, as with Broadwell in late 2014) and every "tock" designated a new microarchitecture. [1] These occurred roughly every year to 18 months. [1]
Due to the slowing rate of process improvements, in 2014 Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture [2] not considered a new generation in and of itself. In March 2016, Intel announced in a Form 10-K report that it would always do this in future, deprecating the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization. [3]
After introducing the Skylake architecture on a 14 nm process in 2015, its first optimization was Kaby Lake in 2016. Intel then announced a second optimization, Coffee Lake, in 2017 [4] making a total of four generations at 14 nm [5] before the Palm Cove die shrink to 10 nm in 2018.
Change (step) | Fabrication process | Micro- architecture | Code names for step | Intel Generation Desktop/Mobile | Intel Generation Xeon | Intel Microcode shortcut(s) Desktop/WS [6] [7] | Intel Microcode shortcut(s) Xeon/Server | Release date | Processors | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
8P/4P Server | 4P/2P Server/WS | Embedded Xeon | 1P Xeon | Enthusiast/WS | Desktop | Mobile | |||||||||
Tick (new fabrica- tion process) | 65 nm | P6, NetBurst | Yonah (P6), Presler (NetBurst), Cedar Mill (NetBurst) | — | 1995-11-1 (P6), 2000-11-20 (NetBurst) | — | — | — | Presler (NetBurst) | Cedar Mill (NetBurst) | Yonah (P6) | ||||
Tock (new micro- architecture) | Core | Merom [8] | 2006-07-27 [9] [10] | Tigerton | Woodcrest Clovertown | Kentsfield | Conroe | Merom | |||||||
Tick | 45 nm | Penryn | 2007-11-11 [11] | Dunnington | Harpertown | Yorkfield | Wolfdale | Penryn | |||||||
Tock | Nehalem | Nehalem | 1 | — | NHM [12] | — | 2008-11-17 [13] | Beckton | Gainestown | Lynnfield | Bloomfield | Lynnfield | Clarksfield | ||
Tick | 32 nm | Westmere | 1 | WSM [12] | 2010-01-04 [14] [15] | Westmere-EX | Westmere-EP | — | Gulftown | Clarkdale | Arrandale | ||||
Tock | Sandy Bridge | Sandy Bridge | 2 | 1 (E3/E5) | SNB | JKT (Jaketown) | 2011-01-09 [16] | Skipped [17] | Sandy Bridge-EP | Gladden | Sandy Bridge | Sandy Bridge-E | Sandy Bridge | Sandy Bridge-M | |
Tick | 22 nm [18] | Ivy Bridge | 3 | 2 (E3/E5/E7) | IVB | IVT (Ivytown) | 2012-04-29 | Ivy Bridge-EX [19] | Ivy Bridge-EP [19] | Gladden | Ivy Bridge | Ivy Bridge-E [20] | Ivy Bridge | Ivy Bridge-M | |
Tock | Haswell | Haswell | 4 | 3 (E3/E5/E7) | HSW, CRW (Crystal Well) with Iris Pro [21] [22] | HSX | 2013-06-02 | Haswell-EX | Haswell-EP | — | Haswell-DT | Haswell-E | Haswell-DT [23] | Haswell-MB (notebooks) Haswell-LP (ultrabooks) [23] | |
Refresh | Haswell Refresh, Devil's Canyon [24] | — | — | 2014-05-11, 2014-06-02 | No server version released | Devil's Canyon | No mobile version released | ||||||||
Tick (Process) | 14 nm [18] | Broadwell [25] | 5 | 4 (E3/E5/E7) | BDW | BDX | 2014-09-05 | Broadwell-EX [26] | Broadwell-EP [26] | Broadwell-DE | Broadwell-DT | Broadwell-E | Broadwell-DT | Broadwell-H Broadwell-U Broadwell-Y | |
Tock (Architecture) | Skylake [25] | Skylake [25] | 6 | 5 (E3) 1 (SP) W-2100 W-31xx | SKL SKL-S SKL-X SKL-H SKL-U SKL-Y SKL-D SKL-DT | SKX | 2015-08-05 [27] | Skylake-SP | Skylake-DE | Skylake-D/DT/H | Skylake-X | Skylake | Skylake-H Skylake-U Skylake-Y | ||
Optimization (Refresh) [3] [28] [29] [30] | Kaby Lake [31] | 7 | 6 (E3) | KBL | — | 2017-01-03 [32] | Only 1P server (Xeon E3) version released | Kaby Lake-DT/H cores: 4 (4/8) | Kaby Lake-X [33] | Kaby Lake | Kaby Lake-H Kaby Lake-U Kaby Lake-Y | ||||
Kaby Lake R [34] [35] | 8 | — | KBL-R | 2017-08-21 [35] | Only mobile version released | Kaby Lake R | |||||||||
Coffee Lake | 8 [36] | E-2100 | CFL CFL-S CFL-E CFL-H CFL-U | 2017-10-05 [37] | Only 1P server (Xeon E) version released | Coffee Lake-H | Coffee Lake-S WS (Coffee Lake-E) | No WS version released | Coffee Lake-S | Coffee Lake-H Coffee Lake-U | |||||
Whiskey Lake, Amber Lake [38] | 8 | — | WHL AML | 2018-08-28 [38] | Only mobile version released | Whiskey Lake-U Amber Lake-Y | |||||||||
Skylake (Skylake-X Refresh) | 9 | ? | 2018-10-08 [39] | Only WS version released | Skylake X | Only WS version released | |||||||||
Coffee Lake (Coffee Lake Refresh) | 9 [36] | E-2200 | CFL-R CFL-ER CFL-HR | — | 2018-10-08, [40] 2019-04-23 [41] | Only 1P server (Xeon E) version released | Coffee Lake-S WS (Coffee Lake-ER) | No WS version released | Coffee Lake-R | Coffee Lake-H Refresh | |||||
Cascade Lake | 10 | 2 (SP) W-2200 W-3200 | CSL | CXL | 2019-04-02 [42] | Cascade Lake-SP | Cascade Lake-AP | — | Cascade Lake-W Cascade Lake-X | Only server / WS version released | |||||
Comet Lake, [43] Amber Lake | 10 | — | CML AML | — | 2019-08-21 [43] | No server version released | Comet Lake-W | Comet Lake-S | Comet Lake-H Comet Lake-U Amber Lake-Y | ||||||
Cascade Lake (Cascade Lake Refresh) | — | 2 (SP) | — | ? | 2020-02-24 [44] | Cascade Lake R | Only server version released | ||||||||
Cooper Lake | — | 3 (SP) | — | CPL CPL-SP | 2020-06-18 [45] | Cooper Lake-SP | Only 8P/4P server version released | ||||||||
Architecture | Cypress Cove [46] | Rocket Lake [46] | 11 | E-2300 | RKL | — | 2021-03-30 [47] | — | Rocket Lake-E | Rocket Lake-W | Rocket Lake-S | — | |||
Process | 10 nm | Palm Cove | Cannon Lake | 8 | — | CNL | 2018-05-16 [48] | Only mobile version released | Cannon Lake-U | ||||||
Architecture | Sunny Cove | Ice Lake [49] | 10 | 3 (SP) | ICL | ICX [50] ICL-SP [50] | 2019-08-01 [51] | — | Ice Lake-SP (2021-04-06) [50] | Ice Lake-D (April 2021) | — | Ice Lake-U Ice Lake-Y | |||
Optimization [30] | Willow Cove | Tiger Lake [30] | 11 | — | TGL | — | 2020-09-02 [52] | Only mobile version released | Tiger Lake-H35 Tiger Lake-UP3 Tiger Lake-UP4 | ||||||
Architecture | Intel 7 | Golden Cove | Alder Lake | 12 | ADL | 2021-11-04 | No server / WS version released | Alder Lake-S | Alder Lake-HX Alder Lake-H Alder Lake-P Alder Lake-U | ||||||
Sapphire Rapids [53] | — | 4 (SP) W-2400 W-3400 | — | SPR | 2023-01-10 | Sapphire Rapids-SP | Sapphire Rapids-HBM Sapphire Rapids-SP | — | Sapphire Rapids-WS | Only server / WS version released | |||||
Optimization | Raptor Cove | Raptor Lake | 13 | — | RPL | — | 2022-10-20 | No server / WS version released | Raptor Lake-S | Raptor Lake-HX Raptor Lake-H Raptor Lake-P Raptor Lake-U | |||||
Raptor Lake [54] (Raptor Lake Refresh) | 14 | E-2400 | RPL-R | 2023-10-17 | Only 1P server (Xeon E) version released | Raptor Lake-E | — | Raptor Lake-S Refresh | — | ||||||
— | 2024-01-08 | Mobile processors refreshed | Raptor Lake-HX Refresh | ||||||||||||
Core Series 1 | Raptor Lake-U Refresh | ||||||||||||||
Emerald Rapids | — | 5 (SP) | — | EMR | 2023-12-14 | Emerald Rapids-SP | Only server version released | ||||||||
Tick | Intel 4 [55] | Redwood Cove | Meteor Lake [56] | Core Ultra (Series 1) | — | MTL | — | 2023-12-14 | Only mobile version released | Meteor Lake-H Meteor Lake-U | |||||
Tick | Intel 3 | Granite Rapids [57] | — | Xeon 6 (SP) | — | GNR | 2024-09-24 [58] | — | Granite Rapids-AP | — | Only server / WS version released | ||||
2025 Q1 [58] [59] | Granite Rapids-SP | ||||||||||||||
2025 [60] | — | Granite Rapids-D | |||||||||||||
Tick | Intel 20A | Lion Cove | Arrow Lake [61] | 15 (informally) Core Ultra 200S Core Ultra (Series 2) | — | ARL | — | 2024-10-03[ disputed – discuss ] | No server / WS version released | Arrow Lake-S | — | ||||
Core Ultra 200H Core Ultra 200HX Intel Core Ultra H & HX Series [62] | 2025 Q1 [62] | — | Arrow Lake-HX Arrow Lake-H | ||||||||||||
Tick | Intel 18A | Lunar Lake | Core Ultra 200V Core Ultra (Series 2) | — | LNL | — | 2024-09-03[ disputed – discuss ] | Only mobile version released | Lunar Lake-V | ||||||
Change (step) | Fabrication process | Micro- architecture | Code names for step | Intel Generation Desktop | Intel Generation Xeon | Intel Microcode shortcut(s) Desktop/WS [6] [7] | Intel Microcode shortcut(s) Xeon/Server | Release date | 8P/4P Server | 4P/2P Server/WS | Embedded Xeon | 1P Xeon | Enthusiast/WS | Desktop | Mobile |
Processors |
With Silvermont Intel tried to start Tick-Tock in Atom architecture but problems with the 10 nm process did not allow to do this. In the table below instead of Tick-Tock steps Process-Architecture-Optimization are used. There is no official confirmation that Intel uses Process-Architecture-Optimization for Atom but it allows us to understand what changes happened in each generation.
Change | Fabrication process | Micro- architecture (Abbr.) [12] | Code names for step | Release date | Processors/SoCs | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|
MID, Smartphone | Tablet | Netbook | Nettop | Embedded | Server | CE | |||||
Process / Architecture | 45 nm | Bonnell (BNL) | Bonnell | 2008 | Silverthorne | — | Diamondville | — | — | — | |
Optimization | Bonnell | 2010 | Lincroft | Pineview | Tunnel Creek Stellarton | — | Sodaville Groveland | ||||
Process | 32 nm | Saltwell | 2011 | Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) | Clover Trail (Cloverview) | Cedar Trail (Cedarview) | — | Centerton & Briarwood | Berryville | ||
Process / Architecture | 22 nm | Silvermont (SLM) | Silvermont | 2013 | Merrifield (Tangier) [64] & Moorefield (Anniedale) [65] & Slayton | Bay Trail-T (Valleyview) | Bay Trail-M (Valleyview) | Bay Trail-D (Valleyview) | Bay Trail-I (Valleyview) | Avoton Rangeley | Unknown |
Process | 14 nm [63] | Airmont | 2014 | Binghamton & Riverton | Cherry Trail-T (Cherryview) [66] | Braswell [67] | Denverton Cancelled | Unknown | |||
Architecture | Goldmont [68] (GLM) | Goldmont | 2016 | Broxton Cancelled | Broxton Cancelled Apollo Lake | Apollo Lake | Apollo Lake | Unknown | Denverton | Unknown | |
Architecture | Goldmont Plus (GLM+, GLP) | Goldmont Plus | 2017 | Unknown | Gemini Lake | Gemini Lake | Gemini Lake | Unknown | Unknown | Unknown | |
Optimization | Goldmont Plus | 2019 | Unknown | Gemini Lake Refresh | Gemini Lake Refresh | Gemini Lake Refresh | Unknown | Unknown | Unknown | ||
Process / Architecture | 10 nm | Tremont | Tremont | 2020 | Unknown | Jasper Lake | Jasper Lake | Jasper Lake | Elkhart Lake | Snow Ridge | Unknown |
Architecture | Intel 7 | Gracemont | Gracemont | 2021 | Unknown | Unknown | Alder Lake & Raptor Lake (hybrid) | Unknown | Unknown | ||
Process / Architecture | Intel 4 | Crestmont | Crestmont | 2023 | Unknown | Unknown | Meteor Lake [69] (hybrid) | Sierra Forest-SP Sierra Forest-AP | Unknown |
Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL; [12] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology. [70] In 2018, Intel announced that Knights Landing and all further Xeon Phi CPU models were discontinued. [71] However, Intel's Sierra Forest and subsequent Atom-based Xeon CPUs are likely a spiritual successor to Xeon Phi.
Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations performed on x86 microprocessors. It was introduced on Xeon server processors in February 2002 and on Pentium 4 desktop processors in November 2002. Since then, Intel has included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.
Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for error correction code (ECC) memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Ultra Path Interconnect (UPI) bus, which replaced the older QuickPath Interconnect (QPI) bus.
Intel Core is a line of multi-core central processing units (CPUs) for midrange, embedded, workstation, high-end and enthusiast computer markets marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.
Skylake is Intel's codename for its sixth generation Core microprocessor family that was launched on August 5, 2015, succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a tock in Intel's tick–tock manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Whiskey Lake, and Comet Lake CPUs.
Cannon Lake is Intel's codename for the 9th generation of Core processors based on Palm Cove, a 10 nm die shrink of the Kaby Lake microarchitecture. As a die shrink, Palm Cove is a new process in Intel's process-architecture-optimization execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set.
Broadwell is the fifth generation of the Intel Core processor. It is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell.
LGA 1151, also known as Socket H4, is a type of zero insertion force flip-chip land grid array (LGA) socket for Intel desktop processors which comes in two distinct versions: the first revision which supports both Intel's Skylake and Kaby Lake CPUs, and the second revision which supports Coffee Lake CPUs exclusively.
Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's previous "tick–tock" manufacturing and design model, Kaby Lake represents the optimized step of the newer process–architecture–optimization model. Kaby Lake began shipping to manufacturers and OEMs in the second quarter of 2016, with its desktop chips officially launched in January 2017.
Ice Lake is Intel's codename for the 10th generation Intel Core mobile and 3rd generation Xeon Scalable server processors based on the Sunny Cove microarchitecture. Ice Lake represents an Architecture step in Intel's process–architecture–optimization model. Produced on the second generation of Intel's 10 nm process, 10 nm+, Ice Lake is Intel's second microarchitecture to be manufactured on the 10 nm process, following the limited launch of Cannon Lake in 2018. However, Intel altered their naming scheme in 2020 for the 10 nm process. In this new naming scheme, Ice Lake's manufacturing process is called simply 10 nm, without any appended pluses.
Tiger Lake is Intel's codename for the 11th generation Intel Core mobile processors based on the Willow Cove Core microarchitecture, manufactured using Intel's third-generation 10 nm process node known as 10SF. Tiger Lake replaces the Ice Lake family of mobile processors, representing an optimization step in Intel's process–architecture–optimization model.
Coffee Lake is Intel's codename for its eighth-generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Coffee Lake processors introduced i5 and i7 CPUs featuring six cores and Core i3 CPUs with four cores and no hyperthreading.
Ryzen is a brand of multi-core x86-64 microprocessors, designed and marketed by AMD for desktop, mobile, server, and embedded platforms, based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainstream, enthusiast, server, and workstation segments, and accelerated processing units (APUs), marketed for mainstream and entry-level segments, and embedded systems applications.
Sapphire Rapids is a codename for Intel's server and workstation processors based on the Golden Cove microarchitecture and produced using Intel 7. It features up to 60 cores and an array of accelerators, and it is the first generation of Intel server and workstation processors to use a chiplet design.
Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.
Comet Lake is Intel's codename for its 10th generation Core processors. They are manufactured using Intel's third 14 nm Skylake process revision, succeeding the Whiskey Lake U-series mobile processor and Coffee Lake desktop processor families. Intel announced low-power mobile Comet Lake-U CPUs on August 21, 2019, H-series mobile CPUs on April 2, 2020, desktop Comet Lake-S CPUs April 30, 2020, and Xeon W-1200 series workstation CPUs on May 13, 2020. Comet Lake processors and Ice Lake 10 nm processors are together branded as the Intel "10th Generation Core" family. In March 2021, Intel officially launched Comet Lake-Refresh Core i3 and Pentium CPUs on the same day as the 11th Gen Core Rocket Lake launch. The low-power mobile Comet Lake-U Core and Celeron 5205U CPUs were discontinued on July 7, 2021.
Sunny Cove is a codename for a CPU microarchitecture developed by Intel, first released in September 2019. It succeeds the Palm Cove microarchitecture and is fabricated using Intel's 10 nm process node. The microarchitecture is implemented in 10th-generation Intel Core processors for mobile and third generation Xeon scalable server processors. 10th-generation Intel Core mobile processors were released in September 2019, while the Xeon server processors were released on April 6, 2021.
Rocket Lake is Intel's codename for its 11th generation Core microprocessors. Released on March 30, 2021, it is based on the new Cypress Cove microarchitecture, a variant of Sunny Cove backported to Intel's 14 nm process node. Rocket Lake cores contain significantly more transistors than Skylake-derived Comet Lake cores.
Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's Intel 7 process node, previously referred to as 10 nm Enhanced SuperFin (10ESF).
Emerald Rapids is the codename for Intel's fifth generation Xeon Scalable server processors based on the Intel 7 node. Emerald Rapids CPUs are designed for data centers; the roughly contemporary Raptor Lake is intended for desktop and mobile usage. Nevine Nassif is a chief engineer for this generation.
A yearly product cadence moves the industry forward in a predictable fashion that can be planned in advance.
The Kaby Lake platform will be similar to Skylake platform that launches this year and will act as a platform refresher
We have long known that Intel was planning a 'Skylake Refresh' that has always been on the roadmap between Skylake and Cannonlake, but it appears that refresh might be going by the code name Kaby lake now.
the switch to 10nm manufacturing has been delayed until the second half of 2017.
Today marks the official launch date of the desktop S-series 7th Generation Core processors...
Intel Core i5-8250U, i5-8350U, i7-8550U, and i7-8650U Kaby Lake-R launches today (Source: Intel)
Intel's messaging with its new Ice Lake Xeon Scalable (ICX or ICL-SP) steers away from simple single core or multicore performance, ...
Intel announced the on-time launch of its high-performance [Xeon 6] 'Granite Rapids' 6900P-series models today, with five new models spanning from 72 cores up to 128 cores, ... Intel will launch the more general-purpose P-core Xeon 6 models with 86 or fewer cores in the first quarter of 2025 (more info below). ... Intel's Xeon 6700P[ sic?] series launches today worldwide, and the follow-on models come in Q1 2025. ...
... With the launch of its Granite Rapids Xeons on Tuesday [24 September 2024], Intel is finally closing the gap ... Its 6700P-series parts, due out early next year, will feature up to two compute dies on board sporting up to 86 cores and a maximum of eight memory channels. ... The remainder of Intel's Xeon 6 roadmap, including its monster 288 E-core 6900E processors and four and eight-socket-capable 6700P parts, won't arrive until early next year. ...
Intel confirmed at their MWC 2024 briefings that Granite Rapids D will debut in 2025 as the successor to Ice Lake D for Xeon D edge processors. ...