Tick–tock model

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Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick-tock is a model that refreshes one side of a binary system each release cycle.

Contents

History

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (sometimes introducing new instructions, as with Broadwell, released in late 2014) and every "tock" designated a new microarchitecture. [1] These occurred roughly every year to 18 months. [2] In 2014, Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture [3] not considered a new generation in and of itself.

In March 2016, Intel announced in a Form 10-K report that it deprecated the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization. [4] The first optimization of the Skylake architecture was Kaby Lake. Intel then announced a second optimization, Coffee Lake, [5] making a total of four generations at 14 nm. [6]

Roadmap

Change
(step)
Fabri­cation
process
Micro-
architecture
Code names
for step
Intel
Generation
Desktop
Intel
Generation
Xeon
Intel Microcode
shortcut(s)
Desktop/WS [7] [8]
Intel Microcode
shortcut(s)
Xeon/Server
Release
date
Processors
8P/4P Server4P/2P Server/WSEmbedded Xeon1P XeonEnthusiast/WSDesktopMobile
Tick
(new fabrica-
tion process
)
65 nm P6, NetBurst Presler,
Cedar Mill,
Yonah
1995-11-1 (P6),
2000-11-20 (Netburst)
Presler Cedar Mill Yonah
Tock
(new micro-
architecture
)
Core Merom [9] 2006-07-27 [10] [11] Tigerton Woodcrest
Clovertown
Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11 [12] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 1N/ANHM [13] 2008-11-17 [14] Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 1N/AWSM [13] 2010-01-04 [15] [16] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 21SNBJKT (Jaketown)2011-01-09 [17] (Skipped) [18] Sandy Bridge-EP GladdenSandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm [19] Ivy Bridge 32IVBIVT (Ivytown)2012-04-29Ivy Bridge-EX [20] Ivy Bridge-EP [20] GladdenIvy BridgeIvy Bridge-E [21] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 43HSW, CRW (Crystal Well)
with Iris Pro [22] [23]
HSX2013-06-02Haswell-EXHaswell-EPN/AHaswell-DTHaswell-EHaswell-DT [24] Haswell-MB (notebooks)
Haswell-LP (ultrabooks) [24]
Refresh Haswell Refresh,
Devil's Canyon [25]
4N/AHSW, CRW (Crystal Well)
with Iris Pro [22] [23]
2014-05-11,
2014-06-02
No server version releasedDevil's CanyonNo mobile version
released
Tick 14 nm [19] Broadwell [26] 54BDWBDX2014-09-05Broadwell-EX [27] Broadwell-EP [27] Broadwell-DEBroadwell-DTBroadwell-EBroadwell-DTBroadwell-H
Broadwell-U
Broadwell-Y
Tock Skylake [26] Skylake [26] 65SKLSKX2015-08-05 [28] Skylake-SPSkylake-DESkylake-DT/HSkylake-X Skylake Skylake-H
Skylake-U
Skylake-Y
Optimizations
(refreshes)
[4] [29] [30] [31]
Kaby Lake [32] 76KBL2017-01-03 [33] Only 1P server (Xeon E3) version released Kaby Lake-DT/H
cores: 4 (4/8)
Kaby Lake-X [34] Kaby Lake Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake R [35] [36] 8N/AKBL-R2017-08-21 [36] Only mobile version releasedKaby Lake R
Coffee Lake 8, 9 [37] E-2xxxCFL2017-10-05 [38] Cascade Lake-SP
Cooper Lake (Q2'20)
Cascade Lake-AP Coffee Lake-DT/H
cores: 6 (12)
Skylake-X Refresh Coffee Lake-S
Coffee Lake-R
Coffee Lake-H
Coffee Lake-U
Coffee Lake-H Refresh
Whiskey Lake,
Amber Lake [39]
8N/AWHL
AML
2018-08-28 [39] Only mobile version releasedWhiskey Lake-U
Amber Lake-Y
Comet Lake [40] 10N/ACML2019-08-21 [40] No server version released Comet Lake-W Comet Lake-S Comet Lake-H
Comet Lake-U
Process Cannon Lake 8N/ACNL2018-05-16 [41] Only mobile version releasedCannon Lake-U
ArchitectureCypress Cove [42] Rocket Lake [42] 12N/AN/A1Q21Rocket Lake
10 nm [43] Sunny Cove Ice Lake [44] 10ICL2019-08-01 [45] Ice Lake-SP (1H21) [46] Ice Lake-U
Ice Lake-Y
Optimization [31] Tiger Lake [31] 11N/ATGL2020-09-02 [47] Only mobile version releasedTiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Process Sapphire Rapids [48] Sapphire Rapids (2021)
Architecture 7 nm [43] Granite Rapids
Optimization
Process
Architecture 5 nm [43]
Optimization

Atom roadmap

Atom roadmap [49]
Fabri­cation
process
Micro-
architecture

(Abbr.) [13]
Code names
for step
Release
date
Processors/SoCs
MID, SmartphoneTabletNetbookNettopEmbeddedServerCommunicationCE
Tick 45 nm Bonnell
(BNL)
Bonnell ?2008 Silverthorne N/A Diamondville Tunnel Creek & StellartonN/A Sodaville
Tock Bonnell ?2010 Lincroft Pineview Groveland
Tick 32 nm Saltwell2011Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview)Clover Trail (Cloverview)Cedar Trail (Cedarview)Un­known Centerton & BriarwoodUn­known Berryville
Tick 22 nm Silvermont
(SLM)
Silvermont 2013Merrifield (Tangier) [50] & Moorefield (Anniedale) [51] & SlaytonBay Trail-T (Valleyview)Bay Trail-M (Valleyview)Bay Trail-D (Valleyview)Bay Trail-I (Valleyview)AvotonRangeleyUn­known
Tick 14 nm [49] Airmont2014Binghamton & RivertonCherry Trail-T (Cherryview) [52] Braswell [53] Denverton
Cancelled cross.svgCancelled
Un­knownUn­known
Tock Goldmont [54]
(GLM)
Goldmont 2016Broxton Cancelled cross.svgCancelledBroxton Cancelled cross.svgCancelled
Apollo Lake
Apollo LakeApollo LakeUn­knownDenvertonUn­knownUn­known

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL; [13] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology. [55]

Both

See also

Related Research Articles

Hyper-threading

Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations performed on x86 microprocessors. It was introduced on Xeon server processors in February 2002 and on Pentium 4 desktop processors in November 2002. Since then, Intel has included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.

Pentium Brand of microprocessors produced by Intel

Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel since 1993. In their form as of November 2011, Pentium processors are considered entry-level products that Intel rates as "two stars", meaning that they are above the low-end Atom and Celeron series, but below the faster Intel Core lineup, and workstation Xeon series.

Intel Core Brand name that Intel uses for various mid-range to high-end consumer and business microprocessors

Intel Core are streamlined midrange consumer, workstation and enthusiast computers central processing units (CPU) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level, and bumping the Celeron series of processors to the low end. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn, Wolfdale and Yorkfield, some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Skylake (microarchitecture)

Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a "tock" in Intel's "tick–tock" manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Cannon Lake, Whiskey Lake, and Comet Lake CPUs.

Westmere (microarchitecture)

Westmere is the code name given to the 32 nm die shrink of Nehalem. While sharing the same CPU sockets, Westmere included Intel HD Graphics, while Nehalem did not.

Cannon Lake is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture. As a die shrink, Cannon Lake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set.

Broadwell (microarchitecture)

Broadwell is the fifth model generation of Intel Processor. It's Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell.

Silvermont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. Silvermont forms the basis for a total of four SoC families:

LGA 1151

LGA 1151, also known as Socket H4, is an Intel microprocessor compatible socket which comes in two distinct versions: the first revision which supports both Intel's Skylake and Kaby Lake CPUs, and the second revision which supports Coffee Lake CPUs exclusively.

Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's previous "tick–tock" manufacturing and design model, Kaby Lake represents the optimized step of the newer process–architecture–optimization model. Kaby Lake began shipping to manufacturers and OEMs in the second quarter of 2016, and mobile chips have started shipping while Kaby Lake (desktop) chips were officially launched in January 2017.

Ice Lake is Intel's codename for the 10th generation Intel Core mobile processors based on the new Sunny Cove Core microarchitecture. Ice Lake represents an Architecture step in Intel's Process-Architecture-Optimization model. Ice Lake CPUs are sold together with the 14 nm Comet Lake CPUs as Intel's "10th Generation Core" product family.

Coffee Lake Eighth-generation Intel Core microprocessor family

Coffee Lake is Intel's codename for its eighth generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Coffee Lake processors introduced i5 and i7 CPUs featuring six cores and Core i3 CPUs with four cores and no hyperthreading.

Sapphire Rapids is the Intel CPU microarchitecture based on the 3rd refinement of the 10 nanometer process. It will be used as part of the Eagle Stream server platform in 2021.

Goldmont Plus is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel. The Gemini Lake platform with 14 nm Goldmont Plus core was officially launched on December 11, 2017. Intel launched Gemini Lake Refresh platform on November 4, 2019.

Cascade Lake is an Intel codename for a 14 nanometer server, workstation and enthusiast processor microarchitecture, launched in April 2019. In Intel's Process-Architecture-Optimization model, Cascade Lake is an optimization of Skylake. Intel states that this will be their first microarchitecture to support 3D XPoint-based memory modules. It also features Deep Learning Boost instructions and mitigations for Meltdown and Spectre. Intel officially launched new Xeon Scalable SKUs on February 24, 2020.

Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by an optimization. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.

Whiskey Lake is Intel's codename for a family of third 14 nm generation Skylake low-power mobile processors. Intel announced Whiskey Lake on August 28, 2018.

Comet Lake is Intel's codename for its 10th generation Core microprocessors. They are manufactured using Intel's third 14 nm Skylake process refinement, succeeding the Whiskey Lake U-series mobile processor and Coffee Lake desktop processor families. Intel announced low-power mobile Comet Lake-U CPUs on August 21, 2019, H-series mobile CPUs on April 2, 2020, desktop Comet Lake-S CPUs April 30, 2020, and Xeon W-1200 series workstation CPUs on May 13, 2020. Comet Lake processors and Ice Lake 10 nm processors are together branded as the Intel "10th Generation Core" family.

References

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