Wafer-level packaging

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Texas Instruments TWL6032 in a wafer-level package

Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment.

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny MOS transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Wafer (electronics) thin slice of semiconductor material used in the fabrication of integrated circuits

In electronics, a wafer is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells. The wafer serves as the substrate for microelectronic devices built in and upon the wafer. It undergoes many microfabrication processes, such as doping, ion implantation, etching, thin-film deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and packaged as an integrated circuit.

Chip-scale package

A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.

Contents

Wafer-level packaging consists of extending the wafer fab processes to include device interconnection and device protection processes. Most other kinds of packaging do wafer dicing first, and then put the individual die in a plastic package and attach the solder bumps. Wafer-level packaging involves attaching the top and bottom outer layers of packaging and the solder bumps to integrated circuits while still in the wafer, and then dicing the wafer.

In the context of manufacturing integrated circuits, wafer dicing is the process by which die are separated from a wafer of semiconductor following the processing of the wafer. The dicing process can involve scribing and breaking, mechanical sawing or laser cutting. All methods are typically automated to ensure precision and accuracy. Following the dicing process the individual silicon chips are encapsulated into chip carriers which are then suitable for use in building electronic devices such as computers, etc.

Solder metal alloy used to join together metal pieces with higher melting points

Solder is a fusible metal alloy used to create a permanent bond between metal workpieces. The word solder comes from the Middle English word soudur, via Old French solduree and soulder, from the Latin solidare, meaning "to make solid". In fact, solder must first be melted in order to adhere to and connect the pieces together after cooling, which requires that an alloy suitable for use as solder have a lower melting point than the pieces being joined. The solder should also be resistant to oxidative and corrosive effects that would degrade the joint over time. Solder used in making electrical connections also needs to have favorable electrical characteristics.

There is no single industry-standard method of wafer-level packaging at present.

A major application area of WLPs are smartphones due to the size constraints. For example, the Apple iPhone 5 has at least eleven different WLPs, the Samsung Galaxy S3 has six WLPs and the HTC One X has seven. Functions provided WLPs in smartphones include sensors, power management, wireless, etc. [1] In fact, it has recently been rumored that the iPhone 7 will use fan-out wafer-level packaging technology in order to achieve a thinner and lighter model. [2] [3] [ needs update ]

Smartphone Multi-purpose mobile device

Smartphones are a class of mobile phones and of multi-purpose mobile computing devices. They are distinguished from feature phones by their stronger hardware capabilities and extensive mobile operating systems, which facilitate wider software, internet, and multimedia functionality, alongside core phone functions such as voice calls and text messaging. Smartphones typically include various sensors that can be leveraged by their software, such as a magnetometer, proximity sensors, barometer, gyroscope and accelerometer, and support wireless communications protocols such as Bluetooth, Wi-Fi, and satellite navigation.

iPhone 5 Smartphone developed by Apple Inc. and sixth generation iPhone

The iPhone 5 is a smartphone that was designed and marketed by Apple Inc. It is the sixth generation of the iPhone succeeding the iPhone 4S and preceding the iPhone 5S and iPhone 5C. Formally unveiled as part of a press event on September 12, 2012, it was released on September 21, 2012. The iPhone 5 is the first iPhone to be announced in September and, setting a trend for subsequent iPhone releases, the first iPhone to be completely developed under the guidance of Tim Cook and the last iPhone to be overseen by Steve Jobs.

HTC One X High-end Android device produced by HTC

The HTC One X is a touchscreen-based, slate-sized smartphone designed and manufactured by HTC. It was released running Android 4.0.3, with the HTC Sense 4.0 skin. It was the first HTC phone to be equipped with a quad-core processor, although the XL variant only has the dual-core 1.5 GHz Krait processor. The One X was announced on February 26, 2012 at the Mobile World Congress and was HTC's sixth flagship product, leading the HTC One series from the time of its release through April 2013, when its successor the HTC One (M7) was announced.

Wafer-level chip scale packaging (WL-CSP) is the smallest package currently available on the market and is produced by OSAT (Outsourced Semiconductor Assembly and Test) companies, such as Advanced Semiconductor Engineering (ASE). [4] A WL-CSP or WLCSP package is just a bare Die with a redistribution layer (or I/O pitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like a BGA package. [5]

Advanced Semiconductor Engineering, Inc., also known as ASE Group, is a provider of independent semiconductor assembling and test manufacturing services, with its headquarters in Kaohsiung, Taiwan.

Die (integrated circuit) an unpackaged integrated circuit

A die, in the context of integrated circuits, is a small block of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor through processes such as photolithography. The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a die.

Ball grid array

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

There are two kinds of wafer level packaging: Fan-in and Fan-Out. Fan-in WLCSP packages have an interposer that is the same size as that of the Die, where as Fan-Out WLCSP packages have an interposer that is larger than the Die. [6] [7]

Interposer electrical interface

An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.

In February 2015, it was discovered that a WL-CSP chip in the Raspberry Pi 2 had issues with xenon flashes (or any other bright flashes of longwave light), inducing the photoelectric effect within the chip. [8] Thus, careful consideration concerning exposure to extremely bright light will need to be given with wafer-level packaging.

Photoelectric effect physical phenomenon

The photoelectric effect is the emission of electrons or other free carriers when light hits a material. Electrons emitted in this manner can be called photoelectrons. This phenomenon is commonly studied in electronic physics, as well as in fields of chemistry, such as quantum chemistry and electrochemistry.

See also

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Semiconductor device fabrication manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, particularly the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Dept., Utica, N.Y. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry.

TSMC Taiwanese semiconductor foundry company

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Integrated circuit packaging Final stage of semiconductor device fabrication

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.

A system in package (SiP) or system-in-a-package is a number of integrated circuits enclosed in a single chip carrier package. The SiP performs all or most of the functions of an electronic system, and is typically used inside a mobile phone, digital music player, etc. Dies containing integrated circuits may be stacked vertically on a substrate. They are internally connected by fine wires that are bonded to the package. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together. Systems-in-package are like systems-on-chip (SoC) but less tightly integrated and not on a single semiconductor die.

In the microelectronics industry, a semiconductor fabrication plant is a factory where devices such as integrated circuits are manufactured.

Package on package (PoP) is an integrated circuit packaging method to combine vertically discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras.

Through-silicon via

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits, in microelectronics and nanoelectronics.

Nemotek Technologie

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A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting the package to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

Embedded Wafer Level Ball Grid Array

Embedded Wafer Level Ball Grid Array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.

Fan-out wafer-level packaging integrated circuit packaging technology

Fan-out wafer-level packaging is an integrated circuit packaging technology, and an enhancement of standard wafer-level packaging (WLP) solutions.

Chip on board Circuit board manufacturing technique

Chip on board (COB) is the method of manufacturing where integrated circuits are wired and bonded directly to a printed circuit board. By eliminating the packaging of individual semiconductor devices, the completed product can be more compact, lighter, and less costly. In some cases chip on board construction improves the operation of radio frequency systems by reducing the inductance and capacitance of integrated circuit leads. Chip on board effectively merges two levels of electronic packaging, level 1 (components) and level 2, and may be referred to as a "level 1.5"

References

  1. Korczynski, Ed (May 5, 2014). "Wafer-level packaging of ICs for mobile systems of the future". Semiconductor Manufacturing & Design Community. Archived from the original on August 16, 2018. Retrieved September 24, 2018.
  2. By Aaron Mamiit, Tech Times. “Apple Wants a Slimmer iPhone 7 and Will Reportedly Use Fan-Out Packaging Technology.” April 1, 2016. Retrieved April 8, 2016.
  3. By Yoni Heisler, BGR. “Report details new tech Apple is using to make the iPhone 7 thinner and lighter.” March 31, 2016. Retrieved April 14, 2016.
  4. By Mark LaPedus, Semiconductor Engineering. “Fan-Out Packaging Gains Steam.” November 23, 2015. Retrieved May 23, 2016.
  5. https://www.nxp.com/docs/en/application-note/AN3846.pdf
  6. "Stats ChipPAC - Wafer Level CSP (WLCSP) - a FIWLP Technology". www.statschippac.com.
  7. "WLCSP Overview, Market and Applications". November 11, 2018.
  8. By Leon Spencer, ZDNet. “Raspberry Pi 2 power crashes when exposed to xenon flash.” February 9, 2015. Retrieved February 5, 2016.

Further reading