I/O
 | This section needs expansion. You can help by adding to it. (May 2023) |
System/370-XA introduced a channel subsystem that performed I/O queuing previously done by the operating system.
| History of IBM mainframes, 1952–present |
|---|
| Market name |
| Architecture |
| Designer | IBM |
|---|---|
| Bits | 32-bit |
| Introduced | 1983 |
| Design | CISC |
| Type | Register–Register Register–Memory Memory–Memory |
| Encoding | Variable (2, 4 or 6 bytes long) |
| Branching | Condition code, indexing, counting |
| Endianness | Big |
| Predecessor | System/370 |
| Successor | ESA/370 |
| Registers | |
| General purpose | 16 |
| Floating point | 4 64-bit |
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IBM System/370-XA is an instruction set architecture introduced by IBM in 1983 with the IBM 308X processors. It extends the IBM System/370 architecture to support 31-bit virtual and physical addresses, and includes a redesigned I/O architecture.
In the System/360, other than the 360/67, and System/370 architectures, the general-purpose registers were 32 bits wide, the machine did 32-bit arithmetic operations, and addresses were always stored in 32-bit words, so the architecture was considered 32-bit, but the machines ignored the top 8 bits of the address resulting in 24-bit addressing. Much of System/360's and System/370's large installed code base relied on a 24-bit logical address; In particular, a heavily used machine instruction, LA, Load Address, explicitly cleared the top eight bits of the address being placed in a register. If the 24-bit limit were to be removed, this would create migration problems for existing software.
This was addressed by adding an addressing mode bit to the Program Status Word controlling whether the program runs in 24-bit mode, in which the top eight bits of virtual addresses are ignored, or 31-bit mode, in which only the uppermost bit of virtual addresses are ignored. [2] : 201-202 [1] : 1-2 Several reasons were given for the choice of 31 bits instead of 32 bits:
BXH and BXLE that treated their arguments as signed numbers when doing comparisons (and which was said to be the reason TSS used 31-bit addressing on the Model 67). [4] : 26, note 85 Certain machine instructions in this 31-bit addressing mode alter the addressing mode bit. For example, the original subroutine call instructions BAL, Branch and Link, and its register-register equivalent, BALR, Branch and Link Register, store certain status information, the instruction length code, [lower-alpha 1] the condition code and the program mask, in the top byte of the return address. A BAS, Branch and Save, instruction was added to allow 31-bit return addresses. BAS, and its register-register equivalent, BASR, Branch and Save Register, was part of the instruction set of the 360/67, which was the only System/360 model to allow addresses longer than 24 bits. These instructions were maintained, but were modified and extended for 31-bit addressing.
Additional instructions in support of allowing calls between 24-bit-addressing and 31-bit-addressing code include two new register-register call/return instructions which also effect an addressing mode change, BASSM, Branch and Save and Set Mode, [5] the 24/31 bit version of a call where the linkage address including the mode is saved and a branch is taken to an address in a possibly different mode, and BSM, Branch and Set Mode, the 24/31 bit version of a return, where the return is directly to the previously saved linkage address and in its previous mode. Taken together, BASSM and BSM allow 24-bit calls to 31-bit (and return to 24-bit), 31-bit calls to 24-bit (and return to 31-bit), 24-bit calls to 24-bit (and return to 24-bit) and 31-bit calls to 31-bit (and return to 31-bit). [2] : 202
Like BALR 14,15 (the 24-bit-only form of a call), BASSM is used as BASSM 14,15, where the linkage address and mode are saved in register 14, and a branch is taken to the subroutine address and mode specified in register 15. Somewhat similarly to BCR 15,14 (the 24-bit-only form of an unconditional return), BSM is used as BSM 0,14, where 0 indicates that the current mode is not saved (the program is leaving the subroutine, anyway), and a return to the caller at the address and mode specified in register 14 is to be taken. [6]
System/370 initially supported only 24-bit physical addresses; the extended real address feature extended this to 26-bit addresses. [7]
System/370-XA changed the page table entry format to support 19 bits of page frame address; pages are 4 KB in 370-XA, so combining a 19-bit page frame address with a 12-bit offset within the page produces a 31-bit physical address. [1] : 3-25 Channel command words can be in one of two formats, with format 0 being the System/370 format, with a 24-bit data address, and format 1 being an additional format, with a 31-bit data address. [2] : 202 [1] : 1-3
| | This section needs expansion. You can help by adding to it. (May 2023) |
System/370-XA introduced a channel subsystem that performed I/O queuing previously done by the operating system.
BALR and is 01b for a BAL, the high order bit is always guaranteed to be set to 0, thereby indicating 24-bit mode, for BALR and BAL on XA and later systems.
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... the high order bit in the last fullword must be set to one to indicate the end of the list.