Common Electrical I/O

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The Common Electrical I/O (CEI) refers to a series of influential Interoperability Agreements (IAs) that have been published by the Optical Internetworking Forum (OIF). CEI defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s electrical interfaces.

Contents

CEI, the Common Electrical I/O

The Common Electrical I/O (CEI) Interoperability Agreement published by the OIF defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s SerDes interfaces. This CEI specification has defined SerDes interfaces for the industry since 2004, and it has been highly influential. The development of electrical interfaces at the OIF began with SPI-3 in 2000, and the first differential interface was published in 2003. The seventh generation electrical interface, CEI-56G, defines five reaches of 56 Gbit/s interfaces. The OIF completed work on its eighth generation through its CEI-112G project. [1] The OIF has launched its ninth generation with its CEI-224G project. [2] CEI has influenced or has been adopted or adapted in many other serial interface standards by many different standards organizations over its long lifetime. SerDes interfaces have been developed based on CEI for most ASIC and FPGA products.

CEI direct predecessors

Throughout the 2000s, the OIF produced an important series of interfaces that influenced the development of multiple generations of devices. Beginning with the donation of the PL-3 interface by PMC-Sierra in 2000, the OIF produced the System Packet Interface (SPI) family of packet interfaces. SPI-3 and SPI-4.2 defined two generations of devices before they were supplanted by the closely related Interlaken standard in the SPI-5 generation in 2006.

The OIF also defined the SerDes Framer Interface (SFI) family of specifications in parallel with SPI. As a part of the SPI-5 and SFI-5 development, a common electrical interface was developed termed SxI-5. SxI-5 abstracted the electrical I/O interface away from the individual SPI and SFI documents. This abstraction laid the groundwork for the highly successful CEI family of Interoperability Agreements and was incorporated in the original release of CEI 1.0 a generation later.

Generations of OIF Electrical Interfaces


Gen.
IA
Title
Pub.
as
Clause
#'s
Max
per pair
Mult.
of bit
rate
per wire
Typical
appli
-cation
Year
pub.
Adopted,
adapted or
influenced
Num.
ranges
Modu-
lations
9CEI-224G232 Gbit/s1160x1600GE thru 200GEIEEE 802.3djPAM-4
8CEI-112GCEI 5.0 [3] 23-4, 26-7116 Gbit/s580x800GE thru 100GE2022IEEE 802.3ck, Infiniband NDR, 128G Fibre Channel and others4PAM-4 and CNRZ-5
7CEI-56GCEI 4.0 [4] [5] 16-2256 Gbit/s290x 400GE thru 50GE2017IEEE 802.3bs and 802.3cd, Infiniband HDR, 64G Fibre Channel 5NRZ, PAM-4 and ENRZ
6.5CEI-28G (added 25G LR)CEI 3.1 [6] 1128 Gbit/s (25 for LR)140x100GE thru 25GE2011 InfiniBand EDR, 32G Fibre Channel, SATA 3.2, IEEE 802.3 100GBASE-KR4, 100GBASE-CR4 and CAUI4, SAS-4, Interlaken 1.94NRZ
6CEI-28GCEI 3.0, [7] 10, 12-1428 Gbit/s140x100GE thru 25GE2008 InfiniBand EDR, 32GFC, SATA 3.2, IEEE 802.3 CAUI4, SAS-4, Interlaken 1.94NRZ
5CEI-11GCEI 2.08-911 Gbit/s55xOC-768, 100GE, 40GE2008InfiniBand QDR, 10GBASE-KR, 10GFC, 16GFC, SAS-3, RapidIO v3, Interlaken3NRZ
4CEI-6GCEI 1.06-76 Gbit/s30x OC-768 (~40 Gbit/s)20044GFC, 8GFC, InfiniBand DDR, SATA 3.0, SAS-2, RapidIO v2, HyperTransport 3.1, Interlaken2NRZ
3SxI-5SxI-5 [8] and CEI 1.04-53.125 Gbit/s16x OC-192, 10GE 2002, 2004 Interlaken, SPI-5, SFI-5, FC 2G, InfiniBand SDR, XAUI, 10GBASE-KX4, 10GBASE-CX4, SATA 2.0, SAS-1, RapidIO v11NRZ
2 SPI-4.2 SPI-4, 4.2 [9] 0.8 Gbit/s4xOC-48 (2.488 Gbit/s)2001-2HyperTransport 1.031NRZ
1 SPI-3 SPI-30.1 Gbit/s (single ended)1 (ref) OC-12 (0.622 Gbit/s)2000(From PMC-Sierra's PL-3)1NRZ

Two earlier generations in this development path were defined by some of the same individuals at the ATM Forum in 1994 and 1995. These specifications were called UTOPIA Level 1 and 2. These operated at 25 Mbit/s (0.025 Gbit/s) and 50 Mbit/s per wire single ended and were used in OC-3 (155 Mbit/s) applications. [10] PL-3 was a packet extension of the cells carried by those earlier interfaces.

Public demonstrations

Compliant implementations to the draft CEI-56G IAs were demonstrated in the OIF booth at the Optical Fiber Conference in 2015, 2016 and 2017. [11]

Related Research Articles

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The RapidIO architecture is a high-performance packet-switched electrical connection technology. It supports messaging, read/write and cache coherency semantics. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect.

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An optical module is a typically hot-pluggable optical transceiver used in high-bandwidth data communications applications. Optical modules typically have an electrical interface on the side that connects to the inside of the system and an optical interface on the side that connects to the outside world through a fiber optic cable. The form factor and electrical interface are often specified by an interested group using a multi-source agreement (MSA). Optical modules can either plug into a front panel socket or an on-board socket. Sometimes the optical module is replaced by an electrical interface module that implements either an active or passive electrical connection to the outside world. A large industry supports the manufacturing and use of optical modules.

References

  1. ↑ "OIF Launches CEI-112G Project for 100G Serial Electrical Links" (Press release). Businesswire, 30 Aug 2016. 30 August 2016.
  2. ↑ "OIF to Update Industry on Next-Generation Electrical and Optical Interface Projects, including 224 Gbps & Co-Packaging, at DesignCon 2023". OIF, 11 Jan 2023.
  3. ↑ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+, 56G+ and 112G+ bps I/O" (PDF). OIF, May 2022.
  4. ↑ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+, and 56G+ bps I/O" (PDF). OIF, Dec 2017.
  5. ↑ "OIF CEI Technology For 56 Gbps Available For Wider Industry Adoption". OIF, Jan 2018.
  6. ↑ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O" (PDF). OIF, 8 Feb 2014.
  7. ↑ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O" (PDF). OIF, Sept 2011. Archived from the original (PDF) on 2018-01-18. Retrieved 2017-05-08.
  8. ↑ "System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 – 3.125Gbps Parallel Interfaces" (PDF). OIF, Oct 2005. Archived from the original (PDF) on 2018-02-19. Retrieved 2017-05-08.
  9. ↑ "System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices" (PDF). OIF, 15 Oct 2003.[ permanent dead link ]
  10. ↑ "OIF shows 56G electrical interfaces & CFP2-ACO". Gazzettabyte, 25 Mar 2015.
  11. ↑ "ATM Physical Layers" (PDF). Washington University in St. Louis (originally published by Ohio State), ~1998.
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