 | This article does not cite any sources .(December 2009) (Learn how and when to remove this template message) |
Stress-induced leakage current (SILC) is an increase in the gate leakage current of a MOSFET, used in semiconductor physics. It occurs due to defects created in the gate oxide during electrical stressing. SILC is perhaps the largest factor inhibiting device miniaturization. Increased leakage is a common failure mode of electronic devices.
The most well-studied defects assisting in the leakage current are those produced by charge trapping in the oxide. This model provides a point of attack and has stimulated researchers to develop methods to decrease the rate of charge trapping by mechanisms such as nitrous oxide (N2O) nitridation of the oxide.
 | This electronics-related article is a stub. You can help Wikipedia by expanding it. |
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of insulated-gate field-effect transistor (IGFET) that is fabricated by the controlled oxidation of a semiconductor, typically silicon. The voltage of the covered gate determines the electrical conductivity of the device; this ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in November 1959. It is the basic building block of modern electronics, and the most frequently manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.
SILC can refer to:
QBD is the term applied to the charge-to-breakdown measurement of a semiconductor device. It is a standard destructive test method used to determine the quality of gate oxides in MOS devices. It is equal to the total accumulated charge passing through the dielectric layer just before failure. Thus QBD is a measure of time-dependent gate oxide breakdown. As a measure of oxide quality, QBD can also be a useful predictor of product reliability under specified electrical stress conditions.
The threshold voltage, commonly abbreviated as Vth, of a field-effect transistor (FET) is the minimum gate-to-source voltage VGS (th) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.
Deep-level transient spectroscopy (DLTS) is an experimental tool for studying electrically active defects in semiconductors. DLTS establishes fundamental defect parameters and measures their concentration in the material. Some of the parameters are considered as defect "finger prints" used for their identifications and analysis.
Burst noise is a type of electronic noise that occurs in semiconductors and ultra-thin gate oxide films. It is also called random telegraph noise (RTN), popcorn noise, impulse noise, bi-stable noise, or random telegraph signal (RTS) noise.
The term high-κ dielectric refers to a material with a high dielectric constant, as compared to silicon dioxide. High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a silicon dioxide gate dielectric or another dielectric layer of a device. The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending Moore's Law. Sometimes, these materials are called "high-k", instead of "high-κ".
Capacitance–voltage profiling is a technique for characterizing semiconductor materials and devices. The applied voltage is varied, and the capacitance is measured and plotted as a function of voltage. The technique uses a metal–semiconductor junction or a p–n junction or a MOSFET to create a depletion region, a region which is empty of conducting electrons and holes, but may contain ionized donors and electrically active defects or traps. The depletion region with its ionized charges inside behaves like a capacitor. By varying the voltage applied to the junction it is possible to vary the depletion width. The dependence of the depletion width upon the applied voltage provides information on the semiconductor's internal characteristics, such as its doping profile and electrically active defect densities., Measurements may be done at DC, or using both DC and a small-signal AC signal, or using a large-signal transient voltage.
Charge trap flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. It is a type of floating-gate MOSFET memory technology, but differs from the conventional floating-gate technology in that it uses a silicon nitride film to store electrons rather than the doped polycrystalline silicon typical of a floating-gate structure. This approach allows memory manufacturers to reduce manufacturing costs five ways:
Negative-bias temperature instability (NBTI) is a key reliability issue in MOSFETs. NBTI manifests as an increase in the threshold voltage and consequent decrease in drain current and transconductance of a MOSFET. The degradation is often approximated by a power-law dependence on time. It is of immediate concern in p-channel MOS devices (pMOS), since they almost always operate with negative gate-to-source voltage; however, the very same mechanism also affects nMOS transistors when biased in the accumulation regime, i.e. with a negative bias applied to the gate.
Hot carrier injection (HCI) is a phenomenon in solid-state electronic devices where an electron or a “hole” gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The term "hot" refers to the effective temperature used to model carrier density, not to the overall temperature of the device. Since the charge carriers can become trapped in the gate dielectric of a MOS transistor, the switching characteristics of the transistor can be permanently changed. Hot-carrier injection is one of the mechanisms that adversely affects the reliability of semiconductors of solid-state devices.
SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"silicon dioxide"—"silicon", is a cross sectional structure of MOSFET (metal-oxide-semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977. This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays. It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material. A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon"). Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia.
The programmable metallization cell, or PMC, is a non-volatile computer memory developed at Arizona State University. PMC, a technology developed to replace the widely used flash memory, providing a combination of longer lifetimes, lower power, and better memory density. Infineon Technologies, who licensed the technology in 2004, refers to it as conductive-bridging RAM, or CBRAM. CBRAM became a registered trademark of Adesto Technologies in 2011. NEC has a variant called "Nanobridge" and Sony calls their version "electrolytic memory".
Lau Wai Shing, also known as Wai Shing Lau, is a Hong Kong electrical engineer and materials scientist. He worked on both Si-based and III-V based microelectronics.
The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET from the underlying source and drain terminals as well as the conductive channel that connects source and drain when the transistor is turned on. Gate oxide is formed by thermal oxidation of the silicon of the channel to form a thin insulating layer of silicon dioxide. The insulating silicon dioxide layer is formed through a process of self-limiting oxidation, which is described by the Deal-Grove model. A conductive gate material is subsequently deposited over the gate oxide to form the transistor. The gate oxide serves as the dielectric layer so that the gate can sustain as high as 1 to 5 MV/cm transverse electric field in order to strongly modulate the conductance of the channel.
Time-dependent gate oxide breakdown is a failure mechanism in MOSFETs, when the gate oxide breaks down as a result of long-time application of relatively low electric field. The breakdown is caused by formation of a conducting path through the gate oxide to substrate due to electron tunneling current, when MOSFETs are operated close to or beyond their specified operating voltages.
In electronics, leakage is the gradual transfer of electrical energy across a boundary normally viewed as insulating, such as the spontaneous discharge of a charged capacitor, magnetic coupling of a transformer with other components, or flow of current across a transistor in the "off" state or a reverse-polarized diode.
Conductive atomic force microscopy (C-AFM) or current sensing atomic force microscopy (CS-AFM) is a mode in atomic force microscopy (AFM) that simultaneously measures the topography of a material and the electric current flow at the contact point of the tip with the surface of the sample. The topography is measured by detecting the deflection of the cantilever using an optical system, while the current is detected using a current-to-voltage preamplifier. The fact that the CAFM uses two different detection systems is a strong advantage compared to scanning tunneling microscopy (STM). Basically, in STM the topography picture is constructed based on the current flowing between the tip and the sample. Therefore, when a portion of a sample is scanned with an STM, it is not possible to discern if the current fluctutations are related to a change in the topography or to a change in the sample conductivity.
Electronic components have a wide range of failure modes. These can be classified in various ways, such as by time or cause. Failures can be caused by excess temperature, excess current or voltage, ionizing radiation, mechanical shock, stress or impact, and many other causes. In semiconductor devices, problems in the device package may cause failures due to contamination, mechanical stress of the device, or open or short circuits.
Advanced Linear Devices Incorporated, also known as ALD, is a semiconductor device design and manufacturing company based in Sunnyvale, California. The company develops and manufactures precision analog CMOS linear integrated circuits for industrial controls, instrumentation, computers, medical devices, automotive, and telecommunications products. It is best known for its redesign of the 555 timer IC as a low-voltage CMOS device.