General information | |
---|---|
Launched | 2011 [1] |
Designed by | ARM Holdings |
Performance | |
Max. CPU clock rate | 520 MHz to 2.3 GHz |
Cache | |
L1 cache | 8–64 KB/8–64 KB |
L2 cache | Optional, up to 1 MB |
Architecture and classification | |
Instruction set | ARMv7-A |
Physical specifications | |
Cores |
|
History | |
Predecessor(s) | ARM Cortex-A5 |
Successor(s) | ARM Cortex-A53 |
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