CAS latency

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Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available. [1] [2] In asynchronous DRAM, the interval is specified in nanoseconds (absolute time). [3] In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.

Contents

RAM operation background

Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal word line. Sending a logical high signal along a given row enables the MOSFETs present in that row, connecting each storage capacitor to its corresponding vertical bit line. Each bit line is connected to a sense amplifier that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh the row.

When no word line is active, the array is idle and the bit lines are held in a precharged [4] state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.

To access memory, a row must first be selected and loaded into the sense amplifiers. This row is then active, and columns may be accessed for read or write.

The CAS latency is the delay between the time at which the column address and the column address strobe signal are presented to the memory module and the time at which the corresponding data is made available by the memory module. The desired row must already be active; if it is not, additional time is required.

As an example, a typical 1 GiB SDRAM memory module might contain eight separate one-gibibit DRAM chips, each offering 128 MiB of storage space. Each chip is divided internally into eight banks of 227=128 Mibits, each of which composes a separate DRAM array. Each bank contains 214=16384 rows of 213=8192 bits each. One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 13-bit column address.[ citation needed ]

Effect on memory access speed

With asynchronous DRAM, memory was accessed by a memory controller on the memory bus based on a set timing rather than a clock, and was separate from the system bus. [3] Synchronous DRAM, however, has a CAS latency that is dependent upon the clock rate. Accordingly, the CAS latency of an SDRAM memory module is specified in clock ticks instead of absolute time.[ citation needed ]

Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, pipeline stalls can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.

Because modern DRAM modules' CAS latencies are specified in clock ticks instead of time, when comparing latencies at different clock speeds, latencies must be translated into absolute times to make a fair comparison; a higher numerical CAS latency may still be less time if the clock is faster. Likewise, a memory module which is underclocked could have its CAS latency cycle count reduced to preserve the same CAS latency time.[ citation needed ]

Double data rate (DDR) RAM performs two transfers per clock cycle, and it is usually described by this transfer rate. Because the CAS latency is specified in clock cycles, and not transfers (which occur on both the rising and falling edges of the clock), it is important to ensure it is the clock rate (half of the transfer rate) which is being used to compute CAS latency times.[ citation needed ]

Another complicating factor is the use of burst transfers. A modern microprocessor might have a cache line size of 64 bytes, requiring eight transfers from a 64-bit-wide (eight bytes) memory to fill. The CAS latency can only accurately measure the time to transfer the first word of memory; the time to transfer all eight words depends on the data transfer rate as well. Fortunately, the processor typically does not need to wait for all eight words; the burst is usually sent in critical word first order, and the first critical word can be used by the microprocessor immediately.

In the table below, data rates are given in million transfersalso known as megatransfers per second (MT/s), while clock rates are given in MHz, million cycles per second.

Memory timing examples

Memory timing examples (CAS latency only)[ citation needed ][ original research? ]
GenerationTypeData rateTransfer time [lower-alpha 1] Command rate [lower-alpha 2] Cycle time [lower-alpha 3] CAS latencyFirst word [lower-alpha 4] Fourth word [lower-alpha 4] Eighth word [lower-alpha 4]
SDRAM PC100100 MT/s10.000 ns100 MHz10.000 ns220.00 ns50.00 ns90.00 ns
PC133133 MT/s7.500 ns133 MHz7.500 ns322.50 ns45.00 ns75.00 ns
DDR SDRAM DDR-333333 MT/s3.000 ns166 MHz6.000 ns 2.515.00 ns24.00 ns36.00 ns
DDR-400400 MT/s2.500 ns200 MHz5.000 ns 315.00 ns22.50 ns32.50 ns
2.512.50 ns20.00 ns30.00 ns
210.00 ns17.50 ns27.50 ns
DDR2 SDRAM DDR2-400400 MT/s2.500 ns200 MHz5.000 ns 420.00 ns27.50 ns37.50 ns
315.00 ns22.50 ns32.50 ns
DDR2-533533 MT/s1.875 ns266 MHz3.750 ns 415.00 ns20.63 ns28.13 ns
311.25 ns16.88 ns24.38 ns
DDR2-667667 MT/s1.500 ns333 MHz3.000 ns 515.00 ns19.50 ns25.50 ns
412.00 ns16.50 ns22.50 ns
DDR2-800800 MT/s1.250 ns400 MHz2.500 ns 615.00 ns18.75 ns23.75 ns
512.50 ns16.25 ns21.25 ns
4.511.25 ns15.00 ns20.00 ns
410.00 ns13.75 ns18.75 ns
DDR2-10661066 MT/s0.938 ns533 MHz1.875 ns 713.13 ns15.94 ns19.69 ns
611.25 ns14.06 ns17.81 ns
59.38 ns12.19 ns15.94 ns
4.58.44 ns11.25 ns15.00 ns
47.50 ns10.31 ns14.06 ns
DDR3 SDRAM DDR3-10661066 MT/s0.938 ns533 MHz1.875 ns 713.13 ns15.94 ns19.69 ns
DDR3-13331333 MT/s0.750 ns666 MHz1.500 ns 913.50 ns15.75 ns18.75 ns
812.00 ns14.25 ns17.25 ns
710.50 ns12.75 ns15.75 ns
69.00 ns11.25 ns14.25 ns
DDR3-13751375 MT/s0.727 ns687 MHz1.455 ns 57.27 ns9.45 ns12.36 ns
DDR3-16001600 MT/s0.625 ns800 MHz1.250 ns 1113.75 ns15.63 ns18.13 ns
1012.50 ns14.38 ns16.88 ns
911.25 ns13.13 ns15.63 ns
810.00 ns11.88 ns14.38 ns
78.75 ns10.63 ns13.13 ns
67.50 ns9.38 ns11.88 ns
DDR3-18661866 MT/s0.536 ns933 MHz1.071 ns 1010.71 ns12.32 ns14.46 ns
99.64 ns11.25 ns13.39 ns
88.57 ns10.18 ns12.32 ns
DDR3-20002000 MT/s0.500 ns1000 MHz1.000 ns 99.00 ns10.50 ns12.50 ns
DDR3-21332133 MT/s0.469 ns1066 MHz0.938 ns 1211.25 ns12.66 ns14.53 ns
1110.31 ns11.72 ns13.59 ns
109.38 ns10.78 ns12.66 ns
98.44 ns9.84 ns11.72 ns
87.50 ns8.91 ns10.78 ns
76.56 ns7.97 ns9.84 ns
DDR3-22002200 MT/s0.455 ns1100 MHz0.909 ns 76.36 ns7.73 ns9.55 ns
DDR3-24002400 MT/s0.417 ns1200 MHz0.833 ns 1310.83 ns12.08 ns13.75 ns
1210.00 ns11.25 ns12.92 ns
119.17 ns10.42 ns12.08 ns
108.33 ns9.58 ns11.25 ns
97.50 ns8.75 ns10.42 ns
DDR3-26002600 MT/s0.385 ns1300 MHz0.769 ns 118.46 ns9.62 ns11.15 ns
DDR3-26662666 MT/s0.375 ns1333 MHz0.750 ns 1511.25 ns12.38 ns13.88 ns
139.75 ns10.88 ns12.38 ns
129.00 ns10.13 ns11.63 ns
118.25 ns9.38 ns10.88 ns
DDR3-28002800 MT/s0.357 ns1400 MHz0.714 ns 1611.43 ns12.50 ns13.93 ns
128.57 ns9.64 ns11.07 ns
117.86 ns8.93 ns10.36 ns
DDR3-29332933 MT/s0.341 ns1466 MHz0.682 ns 128.18 ns9.20 ns10.57 ns
DDR3-30003000 MT/s0.333 ns1500 MHz0.667 ns 128.00 ns9.00 ns10.33 ns
DDR3-31003100 MT/s0.323 ns1550 MHz0.645 ns 127.74 ns8.71 ns10.00 ns
DDR3-32003200 MT/s0.313 ns1600 MHz0.625 ns 1610.00 ns10.94 ns12.19 ns
DDR3-33003300 MT/s0.303 ns1650 MHz0.606 ns 169.70 ns10.61 ns11.82 ns
DDR4 SDRAM
DDR4-16001600 MT/s0.625 ns800 MHz1.250 ns 1215.00 ns16.88 ns19.38 ns
1113.75 ns15.63 ns18.13 ns
1012.50 ns14.38 ns16.88 ns
DDR4-18661866 MT/s0.536 ns933 MHz1.071 ns 1415.00 ns16.61 ns18.75 ns
1313.93 ns15.54 ns17.68 ns
1212.86 ns14.46 ns16.61 ns
DDR4-21332133 MT/s0.469 ns1066 MHz0.938 ns 1615.00 ns16.41 ns18.28 ns
1514.06 ns15.47 ns17.34 ns
1413.13 ns14.53 ns16.41 ns
DDR4-24002400 MT/s0.417 ns1200 MHz0.833 ns 1714.17 ns15.42 ns17.08 ns
1613.33 ns14.58 ns16.25 ns
1512.50 ns13.75 ns15.42 ns
DDR4-26662666 MT/s0.375 ns1333 MHz0.750 ns 1914.25 ns15.38 ns16.88 ns
1712.75 ns13.88 ns15.38 ns
1612.00 ns13.13 ns14.63 ns
1511.25 ns12.38 ns13.88 ns
139.75 ns10.88 ns12.38 ns
DDR4-28002800 MT/s0.357 ns1400 MHz0.714 ns 1712.14 ns13.21 ns14.64 ns
1611.43 ns12.50 ns13.93 ns
1510.71 ns11.79 ns13.21 ns
1410.00 ns11.07 ns12.50 ns
DDR4-30003000 MT/s0.333 ns1500 MHz0.667 ns 1711.33 ns12.33 ns13.67 ns
1610.67 ns11.67 ns13.00 ns
1510.00 ns11.00 ns12.33 ns
149.33 ns10.33 ns11.67 ns
DDR4-32003200 MT/s0.313 ns1600 MHz0.625 ns 1610.00 ns10.94 ns12.19 ns
159.38 ns10.31 ns11.56 ns
148.75 ns9.69 ns10.94 ns
DDR4-33003300 MT/s0.303 ns1650 MHz0.606 ns 169.70 ns10.61 ns11.82 ns
DDR4-33333333 MT/s0.300 ns1666 MHz0.600 ns 169.60 ns10.50 ns11.70 ns
DDR4-34003400 MT/s0.294 ns1700 MHz0.588 ns 169.41 ns10.29 ns11.47 ns
148.24 ns9.12 ns10.29 ns
DDR4-34663466 MT/s0.288 ns1733 MHz0.577 ns 1810.38 ns11.25 ns12.40 ns
179.81 ns10.67 ns11.83 ns
169.23 ns10.10 ns11.25 ns
DDR4-35333533 MT/s0.283 ns1766 MHz0.566 ns 169.06 ns9.91 ns11.04 ns
158.49 ns9.34 ns10.47 ns
DDR4-36003600 MT/s0.278 ns1800 MHz0.556 ns 1910.56 ns11.39 ns12.50 ns
1810.00 ns10.83 ns11.94 ns
179.44 ns10.28 ns11.39 ns
168.89 ns9.72 ns10.83 ns
158.33 ns9.17 ns10.28 ns
147.78 ns8.61 ns9.72 ns
DDR4-37333733 MT/s0.268 ns1866 MHz0.536 ns 179.11 ns9.91 ns10.98 ns
DDR4-38663866 MT/s0.259 ns1933 MHz0.517 ns 189.31 ns10.09 ns11.12 ns
DDR4-40004000 MT/s0.250 ns2000 MHz0.500 ns 199.50 ns10.25 ns11.25 ns
189.00 ns9.75 ns10.75 ns
178.50 ns9.25 ns10.25 ns
168.00 ns8.75 ns9.75 ns
DDR4-41334133 MT/s0.242 ns2066 MHz0.484 ns 199.19 ns9.92 ns10.89 ns
DDR4-42004200 MT/s0.238 ns2100 MHz0.476 ns 199.05 ns9.76 ns10.71 ns
DDR4-42664266 MT/s0.234 ns2133 MHz0.469 ns 198.91 ns9.61 ns10.55 ns
188.44 ns9.14 ns10.08 ns
177.97 ns8.67 ns9.61 ns
167.50 ns8.20 ns9.14 ns
DDR4-44004400 MT/s0.227 ns2200 MHz0.454 ns 198.64 ns9.32 ns10.23 ns
188.18 ns8.86 ns9.77 ns
177.73 ns8.41 ns9.32 ns
DDR4-46004600 MT/s0.217 ns2300 MHz0.435 ns 198.26 ns8.91 ns9.78 ns
187.82 ns8.48 ns9.35 ns
DDR4-48004800 MT/s0.208 ns2400 MHz0.417 ns 208.33 ns8.96 ns9.79 ns
197.92 ns8.54 ns9.38 ns
DDR5 SDRAM
DDR5-48004800 MT/s0.208 ns2400 MHz0.417 ns 4016.67 ns17.29 ns18.13 ns
3815.83 ns16.46 ns17.29 ns
3615.00 ns15.63 ns16.46 ns
3414.17 ns14.79 ns15.63 ns
DDR5-52005200 MT/s0.192 ns2600 MHz0.385 ns 4015.38 ns15.96 ns16.73 ns
3814.62 ns15.19 ns15.96 ns
3613.85 ns14.42 ns15.19 ns
3413.08 ns13.65 ns14.42 ns
DDR5-56005600 MT/s0.179 ns2800 MHz0.357 ns 4014.29 ns14.82 ns15.54 ns
3813.57 ns14.11 ns14.82 ns
3612.86 ns13.39 ns14.11 ns
3412.14 ns12.68 ns13.39 ns
3010.71 ns11.25 ns11.96 ns
DDR5-60006000 MT/s0.167 ns3000 MHz0.333 ns 4013.33 ns13.83 ns14.50 ns
3812.67 ns13.17 ns13.83 ns
3612.00 ns12.50 ns13.17 ns
3210.67 ns11.17 ns11.83 ns
3010.00 ns10.50 ns11.17 ns
DDR5-62006200 MT/s0.161 ns3100 MHz0.323 ns 4012.90 ns13.39 ns14.03 ns
3812.26 ns12.74 ns13.39 ns
3611.61 ns12.10 ns12.74 ns
DDR5-64006400 MT/s0.156 ns3200 MHz0.313 ns 4012.50 ns12.97 ns13.59 ns
3811.88 ns12.34 ns12.97 ns
3611.25 ns11.72 ns12.34 ns
3410.63 ns11.09 ns11.72 ns
3210.00 ns10.47 ns11.09 ns
DDR5-66006600 MT/s0.152 ns3300 MHz0.303 ns 3410.30 ns10.76 ns11.36 ns
GenerationTypeData rateTransfer timeCommand rateCycle timeCAS latencyFirst wordFourth wordEighth word

Notes

  1. Transfer time = 1 / Data rate.
  2. Command rate = Data rate / 2 for double data rate (DDR), Command rate = Data rate for single data rate (SDR).
  3. Cycle time = 1 / Command rate = 2 × Transfer time.
  4. 1 2 3 Nth word = [(2 × CAS latency) + (N − 1)] × Transfer time.

See also

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References

  1. Stokes, Jon "Hannibal" (1998–2004). "Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM". Ars Technica. Archived from the original on 2012-11-01.
  2. Jacob, Bruce L. (December 10, 2002), Synchronous DRAM Architectures, Organizations, and Alternative Technologies (PDF), University of Maryland
  3. 1 2 Memory technology evolution: an overview of system memory technologies, HP, July 2008
  4. Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (December 4, 2007). DRAM Circuit Design: Fundamental and High-Speed Topics. John Wiley & Sons. ISBN   978-0470184752.