OVPsim

Last updated

OVPsim
Developer(s) Imperas
Stable release
20231026.0 / 26 October 2023;8 days ago (2023-10-26)
Operating system Windows, Linux
Type Emulator
License Proprietary, Apache License version 2.0 for models
Website www.ovpworld.org

OVPsim is a multiprocessor platform emulator (often called a full-system simulator) used to run unchanged production binaries of the target hardware. It has public APIs allowing users to create their own processor, peripheral and platform models. Various models are available as open source. [1] OVPsim is a key component of the Open Virtual Platforms initiative (OVP), [2] an organization created to promote the use of open virtual platforms for embedded software development. OVPsim requires OVP registration to download.

Contents

Licensing

OVPsim is developed and maintained by Imperas. [3] The core simulation platform is proprietary software; it is available free of charge for non-commercial usage. Commercial usage requires a low-cost license from Imperas to cover maintenance. Various processor, peripheral and platform models are available as free software under the Apache License version 2.0.

Details

There are three main components of OVP: open-source models, fast OVPsim simulator, and modeling APIs. These components are designed to make it easy to assemble multi-core heterogeneous or homogeneous platforms with complex memory hierarchies, cache systems and layers of embedded software that can run at hundreds of MIPS on standard desktop PCs. OVPSim is considered instruction accurate, but not cycle-accurate. There are many examples of components, and complete virtual platforms that can boot a Linux Kernel in under 5 seconds at OVP Homepage.

Open source models

Within OVP there are several different model categories. These models are provided as both pre-compiled object code, and as in some cases, source files. OVPsim no longer supplies source code for the ARM and MIPS processor models. Currently there are processor models of ARM (processors using the ARMv4, ARMv5, ARMv6, ARMv7, ARMv8 instruction sets) up to the ARM Cortex-A72MPx4 (and including multi-cluster ARMv8 models with GICv3), Imagination MIPS (processors using MIPS32, MIPS64, microMIPS, nanoMIPS and MIPS R6 instruction sets) up to the microAptiv, interAptiv, proAptiv, and Warrior cores, Synopsys Virage ARC600/ARC700 and ARC EM series, Renesas v850, RH850, RL78 and m16c, PowerPC, Altera Nios II, Xilinx MicroBlaze, RISC-V (models using 32bit RV32I, RV32M, RV32IM, RV32A, RV32IMA, RV32IMAC, RV32F, RV32D, RV32E, RV32EC, RV32C, RV32G, RV32GC, RV32GCN, RV32IMAFD and 64bit RV64I, RV64M, RV64IMAC, RV64F, RV64D, RV64C, RV64G, RV64GC, RV64GCN, RV64IMAFD ISA subsets), Andes Technology N25/NX25, N25F/NX25F, A25/AX25, A25F/AX25F, Microsemi CoreRISCV/MiV-RV32IMA, SiFive E31, E51, U54, U54-MC, Freedom U540, Codasip Series 1, 3, 5, 7 RISC-V cores, Intel NiosV RISC-V core, Texas Instruments TMS320 DSP, and OpenRisc families. The OpenHW Group uses OVPsim as the golden reference for their open source RISC-V CV32E40 and CV32E20 cores. There are also models of many different types of system components including RAM, ROM, cache, and bridge. There are peripheral models such as Ethernet MAC, USB, DMA, UART, and FIFO. Several different pre-built platforms are available, including the most common operating systems [4] ucLinux, Linux, Android, FreeRTOS, Nucleus, Micrium.

One of the main uses of the OVP simulation infrastructure is the ability to create and simulate custom built models—either from scratch, or by using one of the open source models as a starting point. The OVP APIs are tailored to different model types: processors, behavioral models of peripherals, and platforms. There are over 100 source model variants available to download.

OVPsim simulator

The OVPsim simulator is available as an OVP reference and is free for non-commercial usage. The simulator uses dynamic binary translation technology to achieve very high simulation speeds. More than a billion simulated instructions per second is possible, in some cases on regular desktop PC machines. OVPsim is available for x86 Windows and Linux hosts.

OVPsim comes with a GDB RSP (Remote Serial Protocol) interface to allow applications running on simulated processors to be debugged with any standard debugger that supports this GDB RSP interface. OVPsim comes with the Imperas iGui Graphical Debugger and also an Eclipse IDE and CDT interface.

OVPsim can be encapsulated and called from within other simulation environments [5] and comes as standard with interface files for C, C++, and SystemC. [6] OVPsim includes native SystemC TLM2.0 interface files. It is also possible to encapsulate legacy models of processors and behavioral models so that they can be used by OVPsim.

Modeling APIs

OVP models are created using C/C++ APIs. There are three main APIs: OP, VMI, BHM/PPM.

OP

The OP API is designed for controlling, connecting, and observing platforms. This API can be called from C, C++, or SystemC. The platform provides the basic structure of the design and creates, connects, and configures the components. The platform also specifies the address mapping, and software that is loaded on the processors. It is very easy with OP to specify very complex and complete platforms of many different processors, local and shared memories, caches, bus bridges, peripherals and all their complex address maps, interrupts and operating systems and application software.

The OP API superseded the ICM API during 2016. The ICM API is still usable for older platforms.

VMI

Processor modeling is provided by the VMI API. These API functions provide the ability to easily describe the behavior of the processor. A processor model written in C using the VMI decodes the target instruction to be simulated and translates this to native x86 instructions that are then executed on the PC. VMI can be used for modeling 8, 16, 32, and 64 bit architectures. There is an interception mechanism enabling emulation of calls to functions in the application runtime libraries (such as write, fstat etc.) without requiring modification of either the processor model or the simulated application.

PPM & BHM

Behavioral components, peripherals, and the overall environment is modeled using C code and calls to these two APIs. Underlying these APIs is an event based scheduling mechanism to enable modeling of time, events, and concurrency. Peripheral models provide callbacks that are called when the application software running on processors modeled in the platform access memory locations where the peripheral is enabled.

Users

OVPsim is being used by multiple educational establishments to provide a simulation infrastructure for the research of parallel computing platforms, [7] [8] hardware/software co-design, [9] performance analysis of embedded systems, [10] and as the basis of other embedded tool developments.[ citation needed ] It is also leveraged for educational courses to allow students to develop and debug application software and create virtual platforms and new models.

A number of leading commercial organizations also use OVPsim as the basis of their product offerings. The technology was licensed by MIPS [11] Technologies to provide modeling support for their MIPS architecture embedded processor range, features in a partnership with leading processor provider ARM, [12] [13] and is part of the Europractice [14] product range for general access to European universities. A version of OVPsim is used by the RISC-V Foundation's Compliance Working Group [15] as a reference simulator. Leading Semiconductor companies such as Renesas have used the simulator for its processor development work, as disclosed in leading electronic industry publications. [16] It was selected by NEPHRON+, an EU research project, for its software and test development environment. [17] VinChip Systems Inc. of Chennai, India used OpenOCD and OVPsim to develop what may be the first 32-bit processor developed in India. [18] The OVP models and virtual platforms form the basis for other activities being undertaken by Imperas.

Related Research Articles

MIPS is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

<span class="mw-page-title-main">MIPS Technologies</span> American fabless semiconductor design company

ARM is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.

SPIM is a MIPS processor simulator, designed to run assembly language code for this architecture. The program simulates R2000 and R3000 processors, and was written by James R. Larus while a professor at the University of Wisconsin–Madison. The MIPS machine language is often taught in college-level assembly courses, especially those using the textbook Computer Organization and Design: The Hardware/Software Interface by David A. Patterson and John L. Hennessy (ISBN 1-55860-428-6).

OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.

Simics is a full-system simulator or virtual platform used to run unchanged production binaries of the target hardware. Simics was originally developed by the Swedish Institute of Computer Science (SICS), and then spun off to Virtutech for commercial development in 1998. Virtutech was acquired by Intel in 2010. Currently, Simics is provided by Intel in a public release and sold commercially by Wind River Systems, which was in the past a subsidiary of Intel.

Nucleus RTOS is a real-time operating system (RTOS) produced by the Embedded Software Division of Mentor Graphics, a Siemens Business, supporting 32- and 64-bit embedded system platforms. The operating system (OS) is designed for real-time embedded systems for medical, industrial, consumer, aerospace, and Internet of things (IoT) uses. Nucleus was released first in 1993. The latest version is 3.x, and includes features such as power management, process model, 64-bit support, safety certification, and support for heterogeneous computing multi-core system on a chip (SOCs) processors.

Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control.

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<span class="mw-page-title-main">Emulator</span> System allowing a device to imitate another

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References

  1. ↑ "Open Virtual Platforms Component Library". Ovpworld.org. 21 November 2012. Retrieved 8 May 2013.
  2. ↑ "Open Virtual Platforms". Ovpworld.org. 21 November 2012. Retrieved 8 May 2013.
  3. ↑ "Imperas". Imperas. 2 July 2008. Retrieved 10 September 2013.
  4. ↑ "MIPS Linux". Linux MIPS. 24 November 2008. Retrieved 10 September 2013.
  5. ↑ "Cadence Zynq". Cadence. 2 April 2010. Retrieved 10 September 2013.
  6. ↑ "There Could Be Value In The Imperas Models". SystemC.org. 17 February 2010. Retrieved 19 September 2013.
  7. ↑ "Hybrid Simulation Framework for Virtual Prototyping Using OVP, SystemC & SCMLEducation" (PDF). vdtt.iitd.ac.in. 11 January 2009. Retrieved 9 May 2013.
  8. ↑ Pinto, C.; Raghav, S.; Marongiu, A.; Ruggiero, M.; Atienza, D.; Benini, L. (2011). "GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms". 2011 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (PDF). pp. 53–62. doi:10.1109/CCGrid.2011.64. ISBN   978-1-4577-0129-0.
  9. ↑ Nita, I.; Lazarescu, V.; Constantinescu, R. (2009). "A new Hw/Sw co-design method for multiprocessor system on chip applications". 2009 International Symposium on Signals, Circuits and Systems. pp. 1–4. doi:10.1109/ISSCS.2009.5206089. ISBN   978-1-4244-3785-6.
  10. ↑ "Using OVPsim for the power estimation of complex RISC based platforms". www.embedded.com. 16 December 2012. Retrieved 8 May 2013.
  11. ↑ "MIPS Technologies Signs License to Distribute OEM Version of the Imperas OVP Simulator". Bloomberg.com. 24 February 2011. Retrieved 26 June 2013.
  12. ↑ "OVPsim by Imperas Software Ltd". ARM Connected Community. 1 January 2012. Retrieved 26 June 2013.
  13. ↑ "Imperas Preps Fast Models of ARM Cortex-A15 Processor". EETimes. 8 March 2012. Retrieved 19 September 2013.
  14. ↑ "Europractice OVPsim Datasheet" (PDF). EuroPractice. 10 November 2012. Retrieved 10 September 2013.
  15. ↑ "RISC-V Compliance Working Group". riscv.org. 6 June 2018. Retrieved 6 June 2018.
  16. ↑ "Processor Models Aid Automotive Software Testing". EETimes. 14 October 2011. Retrieved 10 September 2013.
  17. ↑ Maxfield, Clive (15 May 2012). "Open Virtual Platforms Selected by EU research project". EE Times .
  18. ↑ "'First' India-developed 32-bit processor debuts". EE Times-India. 24 June 2009. ... VinChip Systems Inc. has released ..., which it claims is the first 32-bit processor to be developed in India. ... Support for virtual prototyping has been provided by the ... OVPsim simulator ...
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