The IBM System/370 (S/370) is a range of IBM mainframe computers announced as the successors to the System/360 family on June 30, 1970. The series mostly maintains backward compatibility with the S/360, allowing an easy migration path for customers; this, plus improved performance, were the dominant themes of the product announcement.
JOVIAL is a high-level programming language based on ALGOL 58, specialized for developing embedded systems. It was a major system programming language through the 1960s and 1970s.
Plessey System 250, also known as PP250, was the first operational computer to implement capability-based addressing, to check and balance the computation as a pure Church–Turing machine. Plessey built the systems for a British Army message routing project.
Radiation hardening is the process of making electronic components and circuits resistant to damage or malfunction caused by high levels of ionizing radiation, especially for environments in outer space, around nuclear reactors and particle accelerators, or during nuclear accidents or nuclear warfare.
LEON is a radiation-tolerant 32-bit central processing unit (CPU) microprocessor core that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. It was originally designed by the European Space Research and Technology Centre (ESTEC), part of the European Space Agency (ESA), without any involvement by Sun. Later versions have been designed by Gaisler Research, under a variety of owners. It is described in synthesizable VHSIC Hardware Description Language (VHDL). LEON has a dual license model: An GNU Lesser General Public License (LGPL) and GNU General Public License (GPL) free and open-source software (FOSS) license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product. The core is configurable through VHDL generics, and is used in system on a chip (SOC) designs both in research and commercial settings.
Memory segmentation is an operating system memory management technique of dividing a computer's primary memory into segments or sections. In a computer system using segmentation, a reference to a memory location includes a value that identifies a segment and an offset within that segment. Segments or sections are also used in object files of compiled programs when they are linked together into a program image and when the image is loaded into memory.
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control.
PicoBlaze is the designation of a series of three free soft processor cores from Xilinx for use in their FPGA and CPLD products. They are based on an 8-bit RISC architecture and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family. The processors have an 8-bit address and data port for access to a wide range of peripherals. The license of the cores allows their free use, albeit only on Xilinx devices, and they come with development tools. Third-party tools are available from Mediatronix and others. Also PacoBlaze, a behavioral and device independent implementation of the cores exists and is released under the BSD License. The PauloBlaze is an open source VHDL implementation under the Apache License.
The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.
The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.
The on-board data handling (OBDH) subsystem of a spacecraft is the subsystem which carries and stores data between the various electronics units and the ground segment, via the telemetry, tracking and command (TT&C) subsystem.
The STAR-2 Bus is a fully redundant, flight-proven, spacecraft bus designed for geosynchronous missions.
The V-11, code-named "Scorpio", is a miniprocessor chip set implementation of the VAX instruction set architecture (ISA) developed and fabricated by Digital Equipment Corporation (DEC).
In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16 bits wide. Also, 16-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. 16-bit microcomputers are microcomputers that use 16-bit microprocessors.
SSETI Express was the first spacecraft to be designed and built by European students and was launched by the European Space Agency. SSETI Express is a small spacecraft, similar in size and shape to a washing machine. On board the student-built spacecraft were three CubeSat picosatellites, extremely small satellites weighing around one kg each. These were deployed one hour and forty minutes after launch. Twenty-one university groups, working from locations spread across Europe and with very different cultural backgrounds, worked together via the internet to jointly create the satellite. The expected lifetime of the mission was planned to be 2 months. SSETI Express encountered an unusually fast mission development: less than 18 months from kick-off in January 2004 to flight-readiness.
The DF-224 is a space-qualified computer used in space missions from the 1980s. It was built by Rockwell Autonetics. As with many spacecraft computers, the design is very redundant, since servicing in space is at best difficult and often impossible. The configuration had three CPUs, one active and two spares. The main memory consisted of six memory units, each with 8K 24-bit words of plated wire memory, with up to 48K words total. Four memory modules could be powered up at one time, resulting in a maximum of 32K words of available memory, though some applications such as the Hubble Space Telescope used fewer memory banks to allow for graceful failure modes. There were three I/O processors, one operational and two backups. The power supply consisted of 6 independent power converters, with overlapping coverage of the operating functions. The processor used fixed-point arithmetic with a two's complement format.
The NASA Standard Spacecraft Computer-1 (NSSC-1) is a computer developed as a standard component for the MultiMission Modular Spacecraft at the Goddard Space Flight Center (GSFC) in 1974. The basic spacecraft was built of standardized components and modules, for cost reduction. The computer had 18 bit wide core memory or plated wire memory; up to 64 k. 18 bits was chosen because it gave more accuracy (x4) for data over a 16 bit machine. Floating point arithmetic was not supported.
The KOMDIV-32 is a family of 32-bit microprocessors developed and manufactured by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences. The manufacturing plant of NIISI is located in Dubna on the grounds of the Kurchatov Institute. The KOMDIV-32 processors are intended primarily for spacecraft applications and many of them are radiation hardened (rad-hard).
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
The AN/AYK-14(V) is a family of computers for use in military weapons systems. It is a general-purpose 16-bit microprogrammed computer, intended for airborne vehicles and missions. Its modular design provides for common firmware and support software. It is still in use on Navy fleet aircraft including the F/A-18, and the AV-8B. The AN/AYK-14(V) family of systems is designed to meet MIL-E-5400 (airborne) requirements.
