ND812

Last updated
ND812
Developer Nuclear Data, Inc.
Type Minicomputer
Release date1970 (1970)
Introductory price$10,000, equivalent to about $70,000in 2020

The 12-bit ND812, produced by Nuclear Data, Inc., was a commercial minicomputer developed for the scientific computing market. Nuclear Data introduced it in 1970 at a price under $10,000 [1] (equivalent to about $70,000in 2020 [2] ).

Contents

Description

ND812 registers
01234567891011(bit position)
Main accumulators
JJ accumulator
KK accumulator
Sub-accumulators
RR accumulator
SS accumulator
Program counter
PCProgram Counter
Status flags
  O Overflow bit
  F Flag bit
Internal registers(not accessible by code)
IR Instruction register
MR Memory register
MAR Memory address register

The architecture has a simple programmed I/O bus, plus a DMA channel. The programmed I/O bus typically runs low to medium-speed peripherals, such as printers, teletypes, paper tape punches and readers, while DMA is used for cathode ray tube screens with a light pen, analog-to-digital converters, digital-to-analog converters, tape drives, disk drives.

The word size, 12 bits, is large enough to handle unsigned integers from 0 to 4095 – wide enough for controlling simple machinery. This is also enough to handle signed numbers from -2048 to +2047. This is higher precision than a slide rule or most analog computers. Twelve bits could also store two six-bit characters (note, six-bit isn't enough for two cases, unlike "fuller" ASCII character set). "ND Code" was one such 6-bit character encoding that included upper-case alphabetic, digit, a subset of punctuation and a few control characters. [3] The ND812's basic configuration has a main memory of 4,096 twelve-bit words with a 2 microsecond cycle time. Memory is expandable to 16K words in 4K word increments. Bits within the word are numbered from most significant bit (bit 11) to least significant bit (bit 0).

The programming model consists of four accumulator registers: two main accumulators, J and K, and two sub accumulators, R and S. A rich set of arithmetic and logical operations are provided for the main accumulators and instructions are provided to exchange data between the main and sub accumulators. Conditional execution is provided through "skip" instructions. A condition is tested and the subsequent instruction is either executed or skipped depending on the result of the test. The subsequent instruction is usually a jump instruction when more than one instruction is needed for the case where the test fails.

Input/Output

The I/O facilities include programmable interrupts with 4-levels of priority that can trap to any location in the first 4K words of memory. I/O can transmit 12 or 24 bits, receive 12 or 24 bits, or transmit and receive 12 bits in a cycle. I/O instructions include 4 bits for creating pulses for peripheral control. I/O peripherals can be attached via 76 signal connector that allows for direct memory access by peripherals. DMA is accomplished by "cycle stealing" from the CPU to store words directly into the core memory system.

Nuclear Data provided interfaces to the following peripherals:

Programming facilities

The ND812 did not have an operating system, just a front panel and run and halt switches. The I/O facility allowed for peripherals to directly load programs into memory while the computer was halted and not executing instructions. Another option was to enter a short loader program that would be used to bootstrap the desired program from a peripheral such as a teletype or paper tape reader. Since core memory is non-volatile, shutting off the computer did not result in data or program loss.

A number of system programs were made available by Nuclear Data for use with the ND812: BASC-12 assembler, symbolic text editor, NUTRAN interpreter, and disk-based symbolic text editor,

BASC-12 Assembler

An assembler called BASC-12 was provided. BASC-12 was a two-pass assembler, with an optional third pass. Pass one generates a symbol table, pass two produces a binary output tape and pass three provides a listing of the program.

A sample of the assembler from the Principles of Programming the ND812 Computer manual is shown below:

/Input two unequal numbers "A" and "B", compare the two numbers /and determine which is larger, and output a literal statement /"A > B", or "B > A" as applicable. / /Input and store values for A & B                 *200 Start,          TIF                     /Clear TTY flag                 JPS     Input           /Get value for A                 STJ     A                 JPS     Input           /Get value for B                 STJ     B / /Determine which of the two values is larger                 LDJ     A                 SBJ     B               /Subtract B from A                 SIP     J               /Test for A positive                 JMP     BRAN            /No! B > A                 LDJ     ABCST           /Yes! A > B                 SKIP                    /Skip next instruction BRAN,           LDJ     BACST / /Set up and output expression /                 JPS     OUT                 STOP                 JMP     START / /Working or data storage area / A,              0                       /Constant A B,              0                       /Constant B ABCST,          AB                      /Address of A > B literal BACST,          BA                      /Address of B > A literal C260,           260                     /ASCII zone constant / /Input routine + ASCII zone strip / Input,          0                       /Entry point                 TIS                 JMP     .-1                 TRF                 TCP                     /Echo input at teletype                 TOS                 JMP     .-1                 SBJ     C260                 JMP@    INPUT / /Output routine - Output ASCII expression / Out,            0                       /Entry point                 STJ     LOOP+1                 LDJ     C5              /Set number of character constant                 STJ     CTR / /Output data loop / Loop,           TWLDJ                 0                 TCP                 TOS                 JMP     .-1                 ISZ     LOOP+1                 DSZ     CTR             /Test for all characters out                 JMP     LOOP            /No                 JMP@    Out             /Return C5,             5 CTR,            0 / /Output messages / AB,             215                 212                 301     /A                 276     />                 302     /B BA,             215                 212                 302     /B                 276     />                 301     /A $                                       /End character

NUTRAN

NUTRAN, a conversational, FORTRAN-like language, was provided. NUTRAN was intended for general scientific programming. A sample of NUTRAN is shown below:

1 PRINT 'INPUT VALUES FOR X AND Y' 2 INPUT X,Y 3 Z=X+Y 4 PRINT 'X+Y= ',Z 5 STOP

An example of the conversational nature of NUTRAN is shown below. > is the command prompt and : is the input prompt.

>1.G INPUT VALUES FOR X AND Y :3 :2 X+Y=    .5000000E  1  >

Instruction formats

The instruction set consists of single and double word instructions. Operands can be immediate, direct or indirect. Immediate operands are encoded directly in the instruction as a literal value. Direct operands are encoded as the address of the operand. Indirect operands encode the address of the word containing a pointer to the operand.

Single word instructions

0345611
OperationD/I+/-Displacement

The displacement and sign bit allow single word instructions to address locations between -63 and +63 of the location of the instruction. Bit 4 of the instruction allows for a choice between indirect and direct addressing. When the displacement is used as an indirect address, the contents of the location which is +/-63 locations from the instruction location is used as a pointer to the actual operand.

Many single word instructions do not reference memory and use bits 4 and 5 as part of the specification of the operation.

Literal format

0345611
OperationInstructionLiteral

Group 1 Format

034567811
0010KJShift RotateShift Count

Group 1 instructions perform arithmetic, logical, exchange and shifting functions on the accumulator registers. This includes hardware multiply and divide instructions. Bit 4 is set if the K register is affected. Bit 5 is set if the J register is affected. Both bits are set of both registers are affected.

Group 2 format

034567891011
0011KJOVComp SetComp Clear0
1
>= 0
< 0
 != 0
!= 0

Group 2 format instructions test for internal conditions of the J and K accumulator registers, manipulate the overflow and flag status bits and provide complement, increment and negation operations on the J and K accumulator registers. Bits 9, 10 and 11 select the condition to be tested.

Two word instructions

02367891011
OperationInstructionIndKJ Acc.Change FieldsMF1MF2
Absolute 12-bit Address

Bit 9, Change Fields, inhibits the absolute address from referencing a different field than the one containing the instruction. When bit 8 is 1, the upper accumulator K is used with the instruction, otherwise the lower accumulator J is used. When bit 7 is 1, indirect addressing is used, otherwise direct addressing is used.

Status Word format

01234567891011
FlagOverflowJPSIntIONLIONAIONBIONHCurrent Execution
MF0MF1MF1MF2MF1MF2

The status register doest not exist as a distinct register. It is the contents of several groups of indicators that are all stored in the J register when desired. The JPS and Int bits hold the current field contents that would be used during a JPS instruction or interrupt. The flag and overflow bits can be set explicitly from the J register contents with the RFOV instruction, but the other bits must be set by distinct instructions.

Subroutines

The ND812 processor provides a simple stack for operands, but doesn't use this mechanism for storing subroutine return addresses. Instead, the return address is stored in the target of the JPS instruction and then the PC register is updated to point to the location following the stored return address. To return from the subroutine, an indirect jump through the initial location of the subroutine restores the program counter to the instruction following the JPS instruction.

Instruction set

Memory reference instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
ANDF2000AND with J, ForwardJ
LDJ5000Load JJ
TWLDJ0500Load JJ
STJ5400Store JMemory
TWSTJ0540Store JMemory
TWLDK0510Load KK
TWSTK0550Store KMemory
ADJ4400Add to JJ, OV
TWADJ0440Add to JJ, OV
SBJ4000Subtract from JJ, OV
TWSBJ0400Subtract from JJ, OV
TWADK0450Add to KK, OV
TWSBK0410Subtract from KK, OV
ISZ3400Increment memory and skip if zeroMemory, PC
TWISZ0340Increment memory and skip if zeroMemory, PC
DSZ3000Decrement memory and skip if zeroMemory, PC
TWDSZ0300Decrement memory and skip if zeroMemory, PC
SMJ2400Skip if memory not equal to JPC
TWSMJ0240Skip if memory not equal to JPC
TWSMK0250Skip if memory not equal to KPC
JMP6000Unconditional jumpPC
TWJMP0600Unconditional jumpPC
JPS6400Jump to subroutineMemory, PC
TWJPS0640Jump to subroutineMemory, PC
XCT7000Execute instruction

Logical operations

Assembler MnemonicOctal CodeDescriptionRegisters Affected
AND J1100Logical AND J,K into JJ
AND K1200Logical AND J,K into KK
AND JK1300Logical AND J,K into J,KJ, K

Arithmetic operations on accumulators

Assembler MnemonicOctal CodeDescriptionRegisters Affected
AJK J1120(J + K) to JJ, OV
NAJK J1130-(J + K) to JJ, OV
SJK J1121(J - K) to JJ, OV
NSJK J1131-(J - K) to JJ, OV
ADR J1122(R + J) to JJ, OV
NADR J1132-(R + J) to JJ, OV
ADS J1124(S + J) to JJ, OV
NADS J1134-(S + J) to JJ, OV
SBR J1123(R - J) to JJ, OV
NSBR J1133-(R - J) to JJ, OV
SBS J1125(S - J) to JJ, OV
NSBS J1135-(S - J) to JJ, OV
AJK K1220(J + K) to KK, OV
NAJK K1230-(J + K) to KK, OV
SJK K1221(J - K) to KK, OV
NSJK K1231-(J - K) to KK, OV
ADR K1222(R + K) to KK, OV
NADR K1232-(R + K) to KK, OV
ADS K1224(S + K) to KK, OV
NADS K1234-(S + K) to KK, OV
SBR K1223(R - K) to KK, OV
NSBR K1233-(R - K) to KK, OV
SBS K1225(S - K) to KK, OV
NSBS K1235-(S - K) to KK, OV
AJK JK1320(J + K) to J,KJ, K, OV
NAJK JK1330(J + K) to J,KJ, K, OV
SJK JK1321(J - K) to J,KJ, K, OV
NSJK JK1331-(J - K) to J,KJ, K, OV
MPY1000Multiply J by K into R, SJ, K, R, S, OV
DIV1001Divide J,K by R into J, KJ, K, R, S, OV

Shift/rotate instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
SFTZ J1140Shift J left NJ
SFTZ K1240Shift K left NK
SFTZ JK1340Shift J,K left NJ, K
ROTD J1160Rotate J left NJ
ROTD K1260Rotate K left NK
ROTD JK1360Rotate J,K left NJ,K

Load and exchange operations

Assembler MnemonicOctal CodeDescriptionRegisters Affected
LJSW1010Load J from switch registerJ
LRF J1101Load R from JR
LJFR1102Load J from RJ
EXJR1103Exchange J and RJ, R
LSFK1201Load S from KS
LKFS1202Load K from SK
EXKS1203Exchange K and SK, S
LKFJ1204Load K from JK
EXJK1374Exchange J and KJ, K
LRSFJK1301Load R, S from J, KR, S
LJKFRS1302Load J, K from R, SJ, K
EXJRKS1303Exchange J, K and R, SJ, K, R, S
LJST1011Load status register into JJ
RFOV1002Read Flag, OV from JJ

Conditional skips

Assembler MnemonicOctal CodeDescriptionRegisters Affected
SIZ J1505Skip if J equals zeroPC
SIZ K1605Skip if K equals zeroPC
SIZ JK1705Skip if both J and K equals zeroPC
SNZ J1501Skip if J not equal zeroPC
SNZ K1601Skip if K not equal zeroPC
SNZ JK1701Skip if J or K not equal zeroPC
SIP J1501Skip if J positivePC
SIP K1602Skip if K positivePC
SIP JK1702Skip if both J and K positivePC
SIN J1506Skip if J negativePC
SIN K1606Skip if J negativePC
SIN JK1706Skip if both J and K negativePC

Clear, complement, increment and set

Assembler MnemonicOctal CodeDescriptionRegisters Affected
CLR J1510Clear JJ
CLR K1610Clear KK
CLR JK1710Clear J, KJ, K
CMP J1520Complement JJ
CMP K1620Complement KK
CMP JK1720Complement J, KJ, K
SET J1530Set J to -1J
SET K1630Set K to -1K
SET JK1730Set J, K to -1J, K

Overflow bit instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
SIZ O1445Skip if overflow zeroPC
SNZ O1441Skip if overflow setPC
CLR O1450Clear overflowOV
CMP O1460Complement overflowOV
SET O1470Set overflowOV

Flag bit instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
SIZ1405Skip if flag zeroPC
SNZ1401Skip if flag setPC
CLR1410Clear flagF
CMP1420Complement flagF
SET1430Set flagF

Increment and negate

Assembler MnemonicOctal CodeDescriptionRegisters Affected
INC J1504Increment JJ
INC K1604Increment KK
INC JK1704Increment J, KJ, K
NEG J1524Negate JJ
NEG K1624Negate KK
NEG JK1724Negate J, KJ, K

Interrupt instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
IONH1004Enable interrupt level H
IONA1006Enable interrupt level A, H
IONB1005Enable interrupt level B, H
IONN1007Enable all interrupt levels
IOFF1003Disable all interrupts

Powerfail logic instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
PION1500Powerfail on
PIOF1600Powerfail off
SKPL1440Skip on power lowPC

Literal instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
ANDL2100AND literal with JJ
ADDL2200Add literal to JJ
SUBL2300Subtract literal from JJ

INT and JPS register instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
LDREG7720Load JPS from J, INT from K
LDJK7721Load JPS to J, INT to KJ, K
RJIB7722Set JPS and INT status

Teletype system

Assembler MnemonicOctal CodeDescriptionRegisters Affected
TIS7404Skip if keyboard readyPC
TIR7402Load keyboard into JJ
TIF7401Keyboard-reader fetch
TRF7403Keyboard read-fetchJ
TOS7414Skip if printer-punch readyPC
TOC7411Clear flag
TCP7413Clear flag, print-punch
TOP7412Print-punch

High-Speed paper tape

Assembler MnemonicOctal CodeDescriptionRegisters Affected
HIS7424Skip HS reader readyPC
HIR7422Clear flag; read HS bufferJ
HIF7421HS reader fetch
HRF7423HS reader read-fetchJ
HOS7434Skip if HS punch readyPC
HOL7432Clear flag; load buffer from J
HOP7431Punch on HS punch
HLP7433Load and punch HS punch

Magnetic cassette tape system

Assembler MnemonicOctal CodeDescriptionRegisters Affected
CSLCT17601Place cassette 1 on-line
CSLCT27602Place cassette 2 on-line
CSLCT37604Place cassette 3 on-line
CSTR0740, 0124Selected TWIO skip if transport readyPC
CSFM0740, 0104Skip on filemarkPC
CSET0740, 0110Skip if transport at end of tapePC
CSNE0740, 0122Skip if no errorPC
CSBT0740, 0130Skip if transport at beginning of tapePC
CCLF0740, 0141Clear all cassette control flags
CWFM0740, 0151Write file mark
CSWR0740, 0152Skip if write readyPC
CWRT0740, 0154Write J into buffer
CSRR0740, 0142Skip if readyPC
CRDT0740, 0144Read buffer into JJ
CHSF0740, 0101High speed forward to EOT
CSPF0740, 0102Space forward to filemark
CHSR0740, 0121High-speed reverse to BOT

Miscellaneous instructions

Assembler MnemonicOctal CodeDescriptionRegisters Affected
STOP0000Stop execution
SKIP1442Unconditional skipPC
IDLE1400One cycle delay
TWIO0740Two-word I/O

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References

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