Noise margin

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In electrical engineering, noise margin is the maximum voltage amplitude of extraneous signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level. [1] It is commonly used in at least two contexts as follows:

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In practice, noise margins are the amount of noise, that a logic circuit can withstand. Noise margins are generally defined so that positive values ensure proper operation, and negative margins result in compromised operation, or outright failure. [3]

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References

  1. "noise margin | JEDEC". www.jedec.org. Retrieved 2019-03-01.
  2. "MIT PowerPoint" (PDF).
  3. 1 2 Gopal., Gopalan, K. (1996). Introduction to digital electronic circuits . Chicago: Irwin. ISBN   0256120897. OCLC   33664747.{{cite book}}: CS1 maint: multiple names: authors list (link)