General information | |
---|---|
Designed by | Indian Institute of Technology, Madras |
Common manufacturer(s) | |
Architecture and classification | |
Application | SoC, development boards, based software platform, IOT |
Instruction set | RISC-V |
Model(s) |
|
SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at Indian Institute of Technology, Madras to develop the first indigenous Indian industrial-grade processor. [1] The aim of SHAKTI initiative includes building an opensource production-grade processor, complete system on chips (SoCs), development boards and SHAKTI based software platform. The primary focus of the team is architecture research to develop SoCs, which is competitive with commercial offerings in the market concerning area, power and performance. All the source codes for SHAKTI are open-sourced under the Modified BSD License. The project was funded by the Ministry of Electronics and Information Technology (MeITY), Government of India. [2] [1]
SHAKTI processors are based on the RISC-V ISA. The processors are designed to have either 22 nm FinFET or 180 nm CMOS technology nodes depending on the manufacturing foundry.
SHAKTI has envisioned a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors".
The E and C-classes core are aimed at Internet of things (IoT), embedded and desktop markets. The processor design is free of any royalty and is open-sourced under the modified BSD License. [3]
E-class and C-class core are both implemented in Bluespec SystemVerilog (BSV) language. [1]
The SHAKTI project aims to build 6 variants of processors based on the RISC-V ISA.
The E-class are 32/64 bit microcontrollers capable of supporting all extensions of the RISC-V ISA, aimed at low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM’s M-class (Cortex-M series) cores. It is capable of running real-time operating systems like FreeRTOS, Zephyr and eChronos. Market segments of E-class processor support smart cards, IoT devices, motor controls and robotic platforms. [4] [5]
E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 General-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral Interface (SPI), 2 universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse-width modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC). [6]
The C-class is a 64-bit controller class of processor, aimed at mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It targets mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc. [4] [5]
C-arty100T is a SoC built around the C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I2C). It is aimed at mid-range application workloads with a very low power consumption and has support for optional memory protection. [7]
The I-class is a 64-bit processor which targets the compute, mobile, storage and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The operational clock frequency of this processor is 1.5-2.5 GHz. The team is currently working on implementing atomics, Memory dependence prediction, Instruction Window/Scheduler optimizations, Implementation of some functional units, Performance analysis/projections, Optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor. [5] [8] [9]
A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are aimed at general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance targets. [8]
The S-Class is a 64-bit superscalar, multi-threaded variant aimed at Desktop and Enterprise server Application. Its supports 2-16 cores with a clock frequency of about 1.2–3 GHz. [8]
The H-class is a 64-bit processor aimed at highly parallel enterprise, HPC and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core. [8]
These are experimental/research projects which focus on developing a high security and fault tolerant processor.
The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks. [10]
The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics. [11]
Two C-class processors (codenamed RIMO and Risecreek) and one E-class processor (Moushik) have been taped-out so far.
RIMO is the code name of the SHAKTI C-class based SoC that has been taped-out at Semi-Conductor Laboratory (SCL) at Mohali using 180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP). [4]
CREEK is the code name of the SHAKTI C-class based SoC that has been taped-out at Intel's Oregon fab using a 22nm FinFET process. The 16mm² chip has been tested to operate at a frequency of up to 350 MHz. The chip has been packaged on a 208-pin Ball Grid Array (BGA). [4]
Moushik is the code name of the SHAKTI E-class based SoC that has been taped-out at SCL using 180 nm process technology. It operates in frequency of 100 MHz and developed along with a motherboard called Ardonyx 1.0. [12]
Some of the features of RIMO and Risecreek are as follows:
There are development boards for both E and C class of processors. The details on the board support for different classes of processors are given below.
Altair Engineering from July 2021, included E-Class processor in its embedded system firmware support portfolio for its global customers. [13]
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit RISC single-chip microcontrollers. AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.
XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM architecture instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE, with some later models designed as system-on-a-chip (SoC). Intel sold the PXA family to Marvell Technology Group in June 2006. Marvell then extended the brand to include processors with other microarchitectures, like Arm's Cortex.
The PowerPC 970, PowerPC 970FX, and PowerPC 970MP are 64-bit PowerPC processors from IBM introduced in 2002. When used in PowerPC-based Macintosh computers, Apple referred to them as the PowerPC G5.
The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.
The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.
PowerQUICC is the name for several PowerPC- and Power ISA-based microcontrollers from Freescale Semiconductor. They are built around one or more PowerPC cores and the Communications Processor Module which is a separate RISC core specialized in such tasks such as I/O, communications, ATM, security acceleration, networking and USB. Many components are System-on-a-chip designs tailor-made for embedded applications.
PWRficient is a microprocessor series by P.A. Semi where the PA6T-1682M was the only one that became an actual product.
The PowerPC e600 is a family of 32-bit PowerPC microprocessor cores developed by Freescale for primary use in high performance system-on-a-chip (SoC) designs with speed ranging over 2 GHz, thus making them ideal for high performance routing and telecommunications applications. The e600 is the continuation of the PowerPC 74xx design.
QorIQ is a brand of ARM-based and Power ISA–based communications microprocessors from NXP Semiconductors. It is the evolutionary step from the PowerQUICC platform, and initial products were built around one or more e500mc cores and came in five different product platforms, P1, P2, P3, P4, and P5, segmented by performance and functionality. The platform keeps software compatibility with older PowerPC products such as the PowerQUICC platform. In 2012 Freescale announced ARM-based QorIQ offerings beginning in 2013.
EFM32 Gecko MCUs are a family of mixed-signal 32-bit microcontroller integrated circuits from Energy Micro based on ARM Cortex-M CPUs, including the Cortex-M0+, Cortex-M3 and Cortex-M4.
The R4200 is a microprocessor designed by MIPS Technologies, Inc. (MTI) that implemented the MIPS III instruction set architecture (ISA). It was also known as the VRX during development. The microprocessor was licensed to NEC, and the company fabricated and marketed it as the VR4200. The first VR4200, an 80 MHz part, was introduced in 1993. A faster 100 MHz part became available in 1994.
Zero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design. The company was the second company to announce a design with 1,000 specialized processing cores on a single integrated circuit.
IBM Power microprocessors are designed and sold by IBM for servers and supercomputers. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The Power line of microprocessors has been used in IBM's RS/6000, AS/400, pSeries, iSeries, System p, System i, and Power Systems lines of servers and supercomputers. They have also been used in data storage devices and workstations by IBM and by other server manufacturers like Bull and Hitachi.
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. A number of companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
The MSP432 is a mixed-signal microcontroller family from Texas Instruments. It is based on a 32-bit ARM Cortex-M4F CPU, and extends their 16-bit MSP430 line, with a larger address space for code and data, and faster integer and floating point calculation than the MSP430. Like the MSP430, it has a number of built-in peripheral devices, and is designed for low power requirements. In 2021, TI confirmed that the MSP432 has been discontinued and "there will be no new MSP432 products".
ESP32 is a series of low-cost, low-power system on a chip microcontrollers with integrated Wi-Fi and dual-mode Bluetooth. The ESP32 series employs either a Tensilica Xtensa LX6 microprocessor in both dual-core and single-core variations, Xtensa LX7 dual-core microprocessor or a single-core RISC-V microprocessor and includes built-in antenna switches, RF balun, power amplifier, low-noise receive amplifier, filters, and power-management modules. ESP32 is created and developed by Espressif Systems, a Chinese company based in Shanghai, and is manufactured by TSMC using their 40 nm process. It is a successor to the ESP8266 microcontroller.
VEGA Microprocessors are a portfolio of indigenous processors developed by C-DAC. The portfolio includes several 32-bit/64-bit Single/Multi-core Superscalar In-order/Out-of-Order high performance processors based on the RISC-V ISA. Also features India's first indigenous 64-bit, superscalar, Out-of-order processor which is the main highlight of this portfolio. The Centre for Development of Advanced Computing (C-DAC) is an autonomous Scientific Society, operating under the Ministry of Electronics and Information Technology (MeitY), Govt. of India. The Microprocessor Development Programme (MDP) was initiated and funded by MeitY with the mission objective to design and develop indigenously, a family of Microprocessors, related IPs and the complete ecosystem to enable fully indigenous product development that meets various requirements in the strategic, industrial and commercial sectors. As part of the project C-DAC has successfully developed the VEGA series of microprocessors in soft IP form, which include32-bit Single-core (In-order), 64-bit Single-core, 64-bit Dual-core (Out-of-order), and 64-bit Quad-core (Out-of-order). These high-performance processors are based on the open-source RISC-V Instruction Set Architecture. The tape out of some of these processor chips have also been planned.