Alewife was a cache coherent multiprocessor developed in the early 1990s by a group led by Anant Agarwal at the Massachusetts Institute of Technology. [1] [2] It was based on a network of up to 512 processing nodes, each of which used the Sparcle computer architecture, [3] which was formed by modifying a Sun Microsystems SPARC CPU to include the APRIL techniques for fast context switches. [4]
The Alewife project was one of two predecessors cited by the creators of the popular Beowulf cluster multiprocessor. [5]
Stephen Byram Furber is a British computer scientist, mathematician and hardware engineer, currently the ICL Professor in the Department of Computer Science at the University of Manchester, UK. After completing his education at the University of Cambridge, he spent the 1980s at Acorn Computers, where he was a principal designer of the BBC Micro and the ARM 32-bit RISC microprocessor. As of 2018, over 100 billion copies of the ARM processor have been manufactured, powering much of the world's mobile computing and embedded systems.
Ken Batcher, full name Kenneth Edward Batcher was an emeritus professor of Computer Science at Kent State University. He also worked as a computer architect at Goodyear Aerospace in Akron, Ohio for 28 years.
Cache only memory architecture (COMA) is a computer memory organization for use in multiprocessors in which the local memories at each node are used as cache. This is in contrast to using the local memories as actual main memory, as in NUMA organizations.
Thread Level Speculation (TLS), also known as Speculative Multithreading, or Speculative Parallelization, is a technique to speculatively execute a section of computer code that is anticipated to be executed later in parallel with the normal execution on a separate independent thread. Such a speculative thread may need to make assumptions about the values of input variables. If these prove to be invalid, then the portions of the speculative thread that rely on these input variables will need to be discarded and squashed. If the assumptions are correct the program can complete in a shorter time provided the thread was able to be scheduled efficiently.
Data parallelism is parallelization across multiple processors in parallel computing environments. It focuses on distributing the data across different nodes, which operate on the data in parallel. It can be applied on regular data structures like arrays and matrices by working on each element in parallel. It contrasts to task parallelism as another form of parallelism.
The International Symposium on Computer Architecture (ISCA) is an annual academic conference on computer architecture, generally viewed as the top-tier in the field. Association for Computing Machinery's Special Interest Group on Computer Architecture and Institute of Electrical and Electronics Engineers Computer Society are technical sponsors.
In computer architecture, memory-level parallelism (MLP) is the ability to have pending multiple memory operations, in particular cache misses or translation lookaside buffer (TLB) misses, at the same time.
James Richard "Jim" Goodman retired as professor of computer science at the University of Auckland in Auckland, New Zealand, and emeritus professor at the University of Wisconsin–Madison.
Anant Agarwal is an Indian computer architecture researcher. He is a professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT), where he led the development of Alewife, an early cache coherent multiprocessor, and also has served as director of the MIT Computer Science and Artificial Intelligence Laboratory. He is the founder and CTO of Tilera, a fabless semiconductor company focusing on scalable multicore embedded processor design. He also serves as the CEO of edX, a joint partnership between MIT and Harvard University that offers free online learning.
The Sparcle is an experimental 32-bit microprocessor chip developed in 1992 by a consortium of MIT, LSI Corporation, and Sun Microsystems. It was an evolution Sun's SPARC RISC architecture with features geared towards "large-scale multiprocessing". The chip was manufactured by LSI.
The Texas Instruments Explorer is a family of Lisp machine computers. These computers were sold by Texas Instruments (TI) in the 1980s. The Explorer is based on a design from Lisp Machines Incorporated, which is based on the MIT Lisp machine. The Explorer was used to develop and deploy artificial intelligence software.
Jacob K. White is the Cecil H. Green Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. He researches fast numerical algorithms for simulation, particularly the simulation of circuits. His work on the FASTCAP program for three-dimensional capacitance calculation and FASTHENRY, a program for three-dimensional inductance calculations, is highly cited. He has also done extensive work on steady-state simulation of analog and microwave circuits. White was a significant early contributor to the development of Spectre and SpectreRF.
Oyekunle Ayinde "Kunle" Olukotun is a British-born Nigerian computer scientist who is the Cadence Design Systems Professor of the Stanford School of Engineering, Professor of Electrical Engineering and Computer Science at Stanford University and the director of the Stanford Pervasive Parallelism Lab. Olukotun is known as the “father of the multi-core processor”, and the leader of the Stanford Hydra Chip Multiprocessor research project. Olukotun's achievements include designing the first general-purpose multi-core CPU, innovating single-chip multiprocessor and multi-threaded processor design, and pioneering multicore CPUs and GPUs, transactional memory technology and domain-specific languages programming models. Olukotun's research interests include computer architecture, parallel programming environments and scalable parallel systems, domain specific languages and high-level compilers.
Tachyon is a parallel/multiprocessor ray tracing software. It is a parallel ray tracing library for use on distributed memory parallel computers, shared memory computers, and clusters of workstations. Tachyon implements rendering features such as ambient occlusion lighting, depth-of-field focal blur, shadows, reflections, and others. It was originally developed for the Intel iPSC/860 by John Stone for his M.S. thesis at University of Missouri-Rolla. Tachyon subsequently became a more functional and complete ray tracing engine, and it is now incorporated into a number of other open source software packages such as VMD, and SageMath. Tachyon is released under a permissive license.
SpiNNaker is a massively parallel, manycore supercomputer architecture designed by the Advanced Processor Technologies Research Group (APT) at the Department of Computer Science, University of Manchester. It is composed of 57,600 processing nodes, each with 18 ARM9 processors and 128 MB of mobile DDR SDRAM, totalling 1,036,800 cores and over 7 TB of RAM. The computing platform is based on spiking neural networks, useful in simulating the human brain.
ACM SIGARCH is the Association for Computing Machinery's Special Interest Group on computer architecture, a community of computer professionals and students from academia and industry involved in research and professional practice related to computer architecture and design. The organization sponsors many prestigious international conferences in this area, including the International Symposium on Computer Architecture (ISCA), recognized as the top conference in this area since 1975. Together with IEEE Computer Society's Technical Committee on Computer Architecture (TCCA), it is one of the two main professional organizations for people working in computer architecture.
Jack Justin Stiffler (1934–2019) was an American electrical engineer, computer scientist and entrepreneur, a Fellow of the Institute of Electrical and Electronics Engineers who made key contributions in the areas of communications and fault-tolerant computing.
Timothy M. Pinkston is an American computer engineer, researcher, educator and administrator whose work is focused in the area of computer architecture. He holds the George Pfleger Chair in Electrical and Computer Engineering and is a Professor of Electrical and Computer Engineering at University of Southern California (USC). He also serves in an administrative role as Vice Dean for Faculty Affairs at the USC Viterbi School of Engineering.
Arun K. Somani is Associate Dean for Research of College of Engineering, Distinguished Professor of Electrical and Computer Engineering and Philip and Virginia Sproul Professor at Iowa State University. Somani is Elected Fellow of Institute of Electrical and Electronics Engineers (IEEE) for “contributions to theory and applications of computer networks” from 1999 to 2017 and Life Fellow of IEEE since 2018. He is Distinguished Engineer of Association for Computing Machinery(ACM) and Elected Fellow of The American Association for the Advancement of Science(AAAS).
Trevor Mudge is a computer scientist, academic and researcher. He is the Bredt Family Chair of Computer Science and Engineering, and Professor of Electrical Engineering and Computer Science at the University of Michigan.