Reliability of microelectronic devices, packaging, system reliability modeling, gate oxide integrity, radiation effects, Flash and DRAM reliability, laser programmable metal interconnect
Awards
Fulbright Senior Researcher/Lecturer (2004–2005), IEEE Senior Member (2003), NASA/ASEE Summer Faculty Research Fellow (1998)
Joseph B. Bernstein (commonly cited as Joseph Bernstein) is an Israeli professor of electrical and electronic engineering at the faculty of engineering, Ariel University[1][2][3]. He is recognized for his research in microelectronic device reliability and the physics of failure[4][5], system-level reliability modeling[6], and failure mechanisms in advanced devices[7][8]. Bernstein directs the Laboratory for Failure Analysis and Reliability of Electronic Systems at Ariel University and heads the university’s VLSI program[2][9].
Bernstein studied electrical engineering at Union College in Schenectady, New York, graduating summa cum laude in 1984[2]. He later completed a master’s degree[10] in electrical engineering and a doctorate[11] in electrical engineering and computer science at the Massachusetts Institute of Technology between 1986 and 1990. He is Jewish[12].
Academic career
After earning his doctorate, Bernstein joined the research staff at MIT Lincoln Laboratory, where he worked from 1990 to 1995[2]. He taught as an adjunct professor at Boston University from 1991 to 1993 before moving to the University of Maryland, College Park, where he was assistant professor in reliability, materials, and nuclear engineering (1995–2001) and associate professor in mechanical engineering (2001–2008)[13][14][2]. He was a visiting associate professor at Tel Aviv University between 2003 and 2005 and held a Fulbright Senior Scholar award during that time[2][15]. From 2006 to 2012 he was professor of engineering at Bar-Ilan University[16], before joining Ariel University in 2012, where he continues to serve as professor of electrical and electronic engineering[1][2].
Research
Bernstein’s research spans a wide range of topics in semiconductor reliability and failure physics[17]. His work includes investigations of gate oxide breakdown[18], hot-carrier effects[19][20], and electromigration[21] in advanced CMOS technologies. He has also studied the reliability of Flash and DRAM memory devices[22] and wide-bandgap semiconductors[23][24][25]. Bernstein has contributed to reliability modeling of complex systems[26][27], including aerospace and defense electronics[28], and developed laser-programmable interconnect technologies used for circuit repair and redundancy[29][30]. He has several patents in his name[31][32][33][34][35][36][37][38].
Books
Bernstein has authored or co-authored several books and technical handbooks on electronics reliability, including:
The Korean Electronics Industry (CRC Press, 1997)[39]
Physics-of-Failure Based Handbook of Microelectronic Systems (RIAC, 2008)[40]
Reliability Prediction from Burn-In Data Fit to Reliability Models (Elsevier Academic Press, 2014)[41]
Reliability Prediction for Microelectronics (WILEY Semiconductors, 2024)[42]
Professional affiliations
At Ariel University, Bernstein directs the Reliable Integrated Electronics Laboratory[2]. He also founded and advises the Israel Electronics Manufacturers Working Group on Reliability (ILTAM), established in 2005[2]. He is a senior member of the Institute of Electrical and Electronics Engineers (IEEE)[3].
Awards
Bernstein has received several professional honors, including recognition as a Fulbright Senior Researcher and Lecturer (2004–2005)[2], election as an IEEE Senior Member (2003)[3], and selection as a NASA/ASEE Summer Faculty Research Fellow at the Jet Propulsion Laboratory (1998)[2].
↑ Gurfinkel, Moshe; Xiong, Hao D.; Cheung, Kin P.; Suehle, John S.; Bernstein, Joseph B.; Shapira, Yoram; Lelis, Aivars J.; Habersat, Daniel; Goldsman, Neil (August 2008). "Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast $I$–$V$ Techniques". IEEE Transactions on Electron Devices. 55 (8): 2004–2012. doi:10.1109/TED.2008.926626. ISSN0018-9383.
↑ Bernstein, J. B.; Bender, E.; Bensoussan, A. (March 2023). "The Correct Hot Carrier Degradation Model". 2023 IEEE International Reliability Physics Symposium (IRPS). IEEE. pp.1–5. doi:10.1109/IRPS48203.2023.10117881. ISBN978-1-6654-5672-2.
↑ Vogel, E.M.; Suehle, J.S.; Edelstein, M.D.; Wang, B.; Chen, Y.; Bernstein, J.B. (June 2000). "Reliability of ultrathin silicon dioxide under combined substrate hot-electron and constant voltage tunneling stress". IEEE Transactions on Electron Devices. 47 (6): 1183–1191. Bibcode:2000ITED...47.1183V. doi:10.1109/16.842960.
↑ Wei Zhang; Bernstein, J.B. (1999). "Electromigration simulation under DC/AC stresses considering microstructure". Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247). IEEE. pp.41–43. doi:10.1109/IITC.1999.787072. ISBN978-0-7803-5174-5.
↑ White, Mark; Qin, Jin; Bernstein, Joseph B. (January 2011). "A study of scaling effects on DRAM reliability". 2011 Proceedings - Annual Reliability and Maintainability Symposium. Lake Buena Vista, FL, USA: IEEE. pp.1–6. doi:10.1109/rams.2011.5754522. ISBN978-1-4244-8857-5.
↑ White, M.; Cooper, M.; Chen, Y.; Bernstein, J. (October 2003). "Impact of junction temperature on microelectronic device reliability and considerations for space applications". IEEE International Integrated Reliability Workshop Final Report, 2003. pp.133–136. doi:10.1109/IRWS.2003.1283320. ISBN0-7803-8157-2.
↑ Shen, Yu-Lin; Suresh, S.; Bernstein, J.B. (March 1996). "Laser linking of metal interconnects: analysis and design considerations". IEEE Transactions on Electron Devices. 43 (3): 402–410. Bibcode:1996ITED...43..402S. doi:10.1109/16.485653. ISSN1557-9646.
↑ Rasera, R.L.; Bernstein, J.B. (1996). "Laser linking of metal interconnect: linking dynamics and failure analysis". IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A. 19 (4): 554–561. Bibcode:1996ITCPA..19..554R. doi:10.1109/95.554937.
↑ US6191486B1,Bernstein, Joseph B.,"Technique for producing interconnecting conductive links",issued 2001-02-20
↑ US5585602A,Bernstein, Joseph B.,"Structure for providing conductive paths",issued 1996-12-17
↑ US5861325A,Bernstein, Joseph B.,"Technique for producing interconnecting conductive links",issued 1999-01-19
↑ US6057221A,Bernstein, Joseph B.&Duan, Zhihui,"Laser-induced cutting of metal interconnect",issued 2000-05-02
↑ US20150039244A1,Bernstein, Joseph,"Failure Rate Estimation From Multiple Failure Mechanisms",issued 2015-02-05
↑ US10746781B2,Bernstein, Joseph B.,"Ring oscillator test circuit",issued 2020-08-18
↑ US20140052392A1,BERNSTEIN, Joseph Barry&Gershman, Israel,"Technique for monitoring structural health of a solder joint in no-leads packages",issued 2014-02-20
↑ US12143110B2,Bernstein, Joseph B.&Aharon, Ilan,"Control circuit for ring oscillator-based power controller",issued 2024-11-12
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