Level-sensitive scan design

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Within the field of electronics Level-sensitive scan design (LSSD) is part of an integrated circuit manufacturing test process. It is a DFT scan design method which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan. [1] 

   ____   |    |  Sin ----|S   |  A ------|>   |   |   Q|---+--------------- Q1  D1 -----|D   |   |  CLK1 ---|>   |   |   |____|   |    ____     |   |    |     +---|S   |  B -------------------|>   |         |   Q|------ Q2 / SOut  D2 ------------------|D   |  CLK2 ----------------|>   |         |____|

In a single latch LSSD configuration, the second latch is used only for scan operation. Allowing it to be used as a second system latch reduces the silicon overhead. [1]

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References

  1. 1 2 This article is based on material taken from Level-sensitive+scan+design at the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.
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