Lookahead carry unit

Last updated November 20, 2024

A lookahead carry unit (LCU) is a logical unit in digital circuit design used to decrease calculation time in adder units and used in conjunction with carry look-ahead adders (CLAs).

4-bit adder

A single 4-bit CLA is shown below:

16-bit adder

By combining four 4-bit CLAs, a 16-bit adder can be created but additional logic is needed in the form of an LCU.

The LCU accepts the group propagate ( $P_{G}$ ) and group generate ( $G_{G}$ ) from each of the four CLAs. $P_{G}$ and $G_{G}$ have the following expressions for each CLA adder:^[1]

P_{G}=P_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}

G_{G}=G_{3}+G_{2}\cdot P_{3}+G_{1}\cdot P_{2}\cdot P_{3}+G_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}

The LCU then generates the carry input for each CLA.

Assume that $P_{i}$ is $P_{G}$ and $G_{i}$ is $G_{G}$ from the i^th CLA then the output carry bits are

C_{4}=G_{0}+P_{0}\cdot C_{0}

C_{8}=G_{4}+P_{4}\cdot C_{4}

C_{12}=G_{8}+P_{8}\cdot C_{8}

C_{16}=G_{12}+P_{12}\cdot C_{12}

Substituting $C_{4}$ into $C_{8}$ , then $C_{8}$ into $C_{12}$ , then $C_{12}$ into $C_{16}$ yields the expanded equations:

C_{4}=G_{0}+P_{0}\cdot C_{0}

C_{8}=G_{4}+G_{0}\cdot P_{4}+C_{0}\cdot P_{0}\cdot P_{4}

C_{12}=G_{8}+G_{4}\cdot P_{8}+G_{0}\cdot P_{4}\cdot P_{8}+C_{0}\cdot P_{0}\cdot P_{4}\cdot P_{8}

C_{16}=G_{12}+G_{8}\cdot P_{12}+G_{4}\cdot P_{8}\cdot P_{12}+G_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}+C_{0}\cdot P_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}

$C_{4}$ corresponds to the carry input into the second CLA; $C_{8}$ to the third CLA; $C_{12}$ to the fourth CLA; and $C_{16}$ to overflow carry bit.

In addition, the LCU can calculate its own propagate and generate:

P_{LCU}=P_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}

G_{LCU}=G_{12}+G_{8}\cdot P_{12}+G_{4}\cdot P_{8}\cdot P_{12}+G_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}

C_{16}=G_{LCU}+C_{0}\cdot P_{LCU}

64-bit adder

By combining 4 CLAs and an LCU together creates a 16-bit adder. Four of these units can be combined to form a 64-bit adder. An additional (second-level) LCU is needed that accepts the propagate ( $P_{LCU}$ ) and generate ( $G_{LCU}$ ) from each LCU and the four carry outputs generated by the second-level LCU are fed into the first-level LCUs.

Related Research Articles

In theoretical physics, a Feynman diagram is a pictorial representation of the mathematical expressions describing the behavior and interaction of subatomic particles. The scheme is named after American physicist Richard Feynman, who introduced the diagrams in 1948. The interaction of subatomic particles can be complex and difficult to understand; Feynman diagrams give a simple visualization of what would otherwise be an arcane and abstract formula. According to David Kaiser, "Since the middle of the 20th century, theoretical physicists have increasingly turned to this tool to help them undertake critical calculations. Feynman diagrams have revolutionized nearly every aspect of theoretical physics." While the diagrams are applied primarily to quantum field theory, they can also be used in other areas of physics, such as solid-state theory. Frank Wilczek wrote that the calculations that won him the 2004 Nobel Prize in Physics "would have been literally unthinkable without Feynman diagrams, as would [Wilczek's] calculations that established a route to production and observation of the Higgs particle."

In computational complexity theory, the class NC (for "Nick's Class") is the set of decision problems decidable in polylogarithmic time on a parallel computer with a polynomial number of processors. In other words, a problem with input size n is in NC if there exist constants c and k such that it can be solved in time $O ((log n) c)$ using $O (n k)$ parallel processors. Stephen Cook coined the name "Nick's class" after Nick Pippenger, who had done extensive research on circuits with polylogarithmic depth and polynomial size.

In CPU design, the use of a sum-addressed decoder (SAD) or sum-addressed memory (SAM) decoder is a method of reducing the latency of the CPU cache access and address calculation. This is achieved by fusing the address generation sum operation with the decode operation in the cache SRAM.

In mathematics, computer science, and logic, rewriting covers a wide range of methods of replacing subterms of a formula with other terms. Such methods may be achieved by rewriting systems. In their most basic form, they consist of a set of objects, plus relations on how to transform those objects.

An adder, or summer, is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used in the arithmetic logic units (ALUs). They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.

In Boolean algebra, any Boolean function can be expressed in the canonical disjunctive normal form (CDNF), minterm canonical form, or Sum of Products as a disjunction (OR) of minterms. The De Morgan dual is the canonical conjunctive normal form (CCNF), maxterm canonical form, or Product of Sums which is a conjunction (AND) of maxterms. These forms can be useful for the simplification of Boolean functions, which is of great importance in the optimization of Boolean formulas in general and digital circuits in particular.

In quantum computing and specifically the quantum circuit model of computation, a quantum logic gate is a basic quantum circuit operating on a small number of qubits. Quantum logic gates are the building blocks of quantum circuits, like classical logic gates are for conventional digital circuits.

In mathematical logic and automated theorem proving, resolution is a rule of inference leading to a refutation-complete theorem-proving technique for sentences in propositional logic and first-order logic. For propositional logic, systematically applying the resolution rule acts as a decision procedure for formula unsatisfiability, solving the Boolean satisfiability problem. For first-order logic, resolution can be used as the basis for a semi-algorithm for the unsatisfiability problem of first-order logic, providing a more practical method than one following from Gödel's completeness theorem.

A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple-carry adder (RCA), for which the carry bit is calculated alongside the sum bit, and each stage must wait until the previous carry bit has been calculated to begin calculating its own sum bit and carry bit. The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger-value bits of the adder.

A carry-skip adder is an adder implementation that improves on the delay of a ripple-carry adder with little effort compared to other adders. The improvement of the worst-case delay is achieved by using several carry-skip adders to form a block-carry-skip adder.

In electronics, a carry-select adder is a particular way to implement an adder, which is a logic element that computes the $-bit sum of two -bit numbers. The carry-select adder is simple but rather fast, having a gate level depth of .$

The Brent–Kung adder, proposed in 1982, is an advanced binary adder design, having a gate level depth of $.$

XOR gate is a digital logic gate that gives a true output when the number of true inputs is odd. An XOR gate implements an exclusive or from mathematical logic; that is, a true output results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false. A way to remember XOR is "must have one or the other but not both".

The Dadda multiplier is a hardware binary multiplier design invented by computer scientist Luigi Dadda in 1965. It uses a selection of full and half adders to sum the partial products in stages until two numbers are left. The design is similar to the Wallace multiplier, but the different reduction tree reduces the required number of gates and makes it slightly faster.

In electronics, a Ling adder is a particularly fast binary adder designed using H. Ling's equations and generally implemented in BiCMOS. Samuel Naffziger of Hewlett-Packard presented an innovative 64 bit adder in 0.5 μm CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4.

A carry-save adder is a type of digital adder, used to efficiently compute the sum of three or more binary numbers. It differs from other digital adders in that it outputs two numbers, and the answer of the original summation can be achieved by adding these outputs together. A carry save adder is typically used in a binary multiplier, since a binary multiplier involves addition of more than two binary numbers after multiplication. A big adder implemented using this technique will usually be much faster than conventional addition of those numbers.

In computer science, the prefix sum, cumulative sum, inclusive scan, or simply scan of a sequence of numbers $x 0, x 1, x 2, ...$ is a second sequence of numbers $y 0, y 1, y 2, ...$ , the sums of prefixes of the input sequence:

In computing, the Kogge–Stone adder is a parallel prefix form of carry-lookahead adder. Other parallel prefix adders (PPA) include the Sklansky adder (SA), Brent–Kung adder (BKA), the Han–Carlson adder (HCA), the fastest known variation, the Lynch–Swartzlander spanning tree adder (STA), Knowles adder (KNA) and Beaumont-Smith adder (BSA).

In electronics, a subtractor – a digital circuit that performs subtraction of numbers – can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend, subtrahend, and a borrow in from the previous bit order position. The outputs are the difference bit and borrow bit $. The subtractor is best understood by considering that the subtrahend and both borrow bits have negative weights, whereas the X and D bits are positive. The operation performed by the subtractor is to rewrite as the sum .$

A truth table is a mathematical table used in logic—specifically in connection with Boolean algebra, Boolean functions, and propositional calculus—which sets out the functional values of logical expressions on each of their functional arguments, that is, for each combination of values taken by their logical variables. In particular, truth tables can be used to show whether a propositional expression is true for all legitimate input values, that is, logically valid.

References

↑ "Carry Look Ahead Adder". Archived from the original on 2011-09-25. Retrieved 2011-10-07.

Katz, Randy (1994). Contemporary Logic Design . The Benjamin/Cummings Publishing Company. pp. 249–256. ISBN 0-8053-2703-7.
Vahid, Frank (2006). Digital Design . John Wiley and Sons Publishers. pp. 296–316. ISBN 0-470-04437-3.

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.

[1] "Carry Look Ahead Adder". Archived from the original on 2011-09-25. Retrieved 2011-10-07.

[1]