In silicon wafer manufacturing overlay control is the control of pattern-to-pattern alignment necessary in the manufacture of silicon wafers.
Silicon wafers are currently manufactured in a sequence of steps, each stage placing a pattern of material on the wafer; in this way transistors, contacts, etc., all made of different materials, are laid down. In order for the final device to function correctly, these separate patterns must be aligned correctly – for example contacts, lines and transistors must all line up.
A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits.
Overlay control has always played an important role in semiconductor manufacturing, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind can cause short circuits and connection failures, which in turn impact fab yield and profit margins.
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
Overlay control has become even more critical now because the combination of increasing pattern density and innovative techniques such as double patterning and 193nm immersion lithography creates a novel set of pattern-based yield challenges at the 45nm technology node and below. This combination causes error budgets to shrink below 30 percent of design rules, where existing overlay metrology solutions cannot meet total measurement uncertainty (TMU) requirements.
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits (ICs) that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor equal to the refractive index of the liquid. Current immersion lithography tools use highly purified water for this liquid, achieving feature sizes below 45 nanometers. ASML and Nikon are currently the only manufacturers of immersion lithography systems. The idea for immersion lithography was first proposed by Burn J. Lin and realized in the 1980s. Immersion lithography is now being extended to sub-20nm nodes through the use of multiple patterning.
Overlay metrology solutions with both higher measurement accuracy/precision and process robustness are key factors when addressing increasingly tighter overlay budgets. Higher order overlay control and in-field metrology using smaller, micro-grating or other novel targets are becoming essential for successful production ramps and higher yields at 45nm and beyond.
Examples of the widely adopted overlay measurement tools worldwide are KLA-Tencor's ARCHER , and the nanometrics CALIPER series, overlay metrology platforms.
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