Semiconductor device fabrication

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NASA's Glenn Research Center clean room Clean room.jpg
NASA's Glenn Research Center clean room

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny MOS transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Electronics physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter

Electronics comprises the physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter.

Photolithography, also called optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a photosensitive chemical photoresist on the substrate. A series of chemical treatments then either etches the exposure pattern into the material or enables deposition of a new material in the desired pattern upon the material underneath the photoresist. In complex integrated circuits, a CMOS wafer may go through the photolithographic cycle as many as 50 times.

Contents

The entire manufacturing process, from start to packaged chips ready for shipment, takes six to eight weeks and is performed in highly specialized facilities referred to as foundries or fabs. [1] In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks (about 4 months) with 11–13 weeks (3 to 4 months) being the industry average. [2] Production in advanced fabrication facilities is completely automated, and carried out in a hermetically sealed, nitrogen environment to improve yield (number of working microchips vs the number of microchips made in a wafer) with FOUPs and automated material handling systems taking care of the transport of wafers from machine to machine.

In the microelectronics industry, a semiconductor fabrication plant is a factory where devices such as integrated circuits are manufactured.

The 14 nanometer MOSFET technology node is the successor to the 22 nm/(20 nm) node. The 14 nm was so named by the International Technology Roadmap for Semiconductors (ITRS). One nanometer (nm) is one billionth of a meter. Until about 2011, the node following 22 nm was expected to be 16 nm. All 14 nm nodes use FinFET technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.

By industry standard, each generation of the semiconductor manufacturing process, also known as "technology node", is designated by the process’s minimum feature size. Technology nodes, also known as "process technologies" or simply "nodes", are typically indicated by the size in nanometers (or historically micrometers) of the process's gate length.[ clarification needed ] Since 2009, however, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. [3] [4] [5] For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. [6] Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm). [7] [8]

Micrometre one millionth of a metre

The micrometre or micrometer, also commonly known by the previous name micron, is an SI derived unit of length equalling 1×10−6 metre ; that is, one millionth of a metre.

GlobalFoundries is an American semiconductor foundry headquartered in Santa Clara, California, United States. GlobalFoundries was created by the divestiture of the manufacturing arm of Advanced Micro Devices (AMD). The Emirate of Abu Dhabi is the owner of the company through its subsidiary Advanced Technology Investment Company (ATIC).

As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018. [9] As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node, [10] with a density of 171.3 million transistors per square millimeter. [11] In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop develompent of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab would be beyond the company's financial abilities. [12]

United Microelectronics Corporation Taiwanese technology company

United Microelectronics Corporation is a Taiwanese company which is based in Hsinchu, Taiwan. It was founded as Taiwan's first semiconductor company in 1980 as a spin-off of the government-sponsored Industrial Technology Research Institute (ITRI).

Micron Technology American multinational corporation based in Boise, Idaho which produces many forms of semiconductor devices.

Micron Technology, Inc. is an American producer of computer memory and computer data storage including dynamic random-access memory, flash memory, and USB flash drives. It is headquartered in Boise, Idaho. Its consumer products are marketed under the brands Crucial and Ballistix. Micron and Intel together created IM Flash Technologies, which produces NAND flash memory. It owned Lexar between 2006 and 2017.

SK Hynix South Korean memory semiconductor supplier

SK Hynix Inc. is a South Korean memory semiconductor supplier of dynamic random-access memory (DRAM) chips and flash memory chips. Hynix is the world's second-largest memory chipmaker and the world's 3rd-largest semiconductor company. Founded as Hyundai Electronic Industrial Co., Ltd. in 1983 and known as Hyundai Electronics, the company has manufacturing sites in Korea, the United States, China and Taiwan. In 2012, when SK Telecom became its major shareholder, Hynix merged to SK Group. The company's shares are traded on the Korea Stock Exchange, and the Global Depository shares are listed on the Luxembourg Stock Exchange.

History

The first MOSFET (metal-oxide-silicon field-effect transistor) semiconductor devices were fabricated by Egyptian engineer Mohamed Atalla and Korean engineer Dawon Kahng at Bell Labs between 1959 and 1960. [13] There were originally two types of MOSFET technology, PMOS (p-type MOS) and NMOS (n-type MOS). [14] Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices with a 20  µm process. [13]

MOSFET Transistor used for amplifying or switching electronic signals.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of field-effect transistor that is fabricated by the controlled oxidation of a semiconductor, typically silicon. It has a covered gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in November 1959. It is the basic building block of modern electronics, and the most widely manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.

Field-effect transistor transistor that uses an electric field to control the electrical behaviour of the device. FETs are also known as unipolar transistors since they involve single-carrier-type operation

The field-effect transistor (FET) is an electronic device which uses an electric field to control the flow of current. FETs are devices with three terminals: source, gate, and drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source.

A semiconductor device is an electronic component that exploits the electronic properties of semiconductor material, principally silicon, germanium, and gallium arsenide, as well as organic semiconductors. Semiconductor devices have replaced vacuum tubes in most applications. They use electrical conduction in the solid state rather than the gaseous state or thermionic emission in a vacuum.

An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. [15] [16] CMOS was commercialised by RCA in the late 1960s. [15] RCA used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years. [17]

CMOS Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuits (ICs), including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

Chih-Tang "Tom" Sah is a Chinese-American engineer. He is best known for inventing CMOS logic with Frank Wanlass at Fairchild Semiconductor in 1963. CMOS is now used in nearly all modern very large-scale integration (VLSI) semiconductor devices.

Dr. Frank Marion Wanlass was an American electrical engineer. He is best known for inventing CMOS logic with Chih-Tang Sah in 1963. CMOS has since become the standard semiconductor device fabrication process for MOSFETs.

Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East. It is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC. [18] They also have facilities spread in different countries.

List of steps

This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order. Equipment for carrying out these processes is made by a handful of companies.

Progress of miniaturisation, and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths. Comparison semiconductor process nodes.svg
Progress of miniaturisation, and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths.

Prevention of contamination and defects

When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big an issue as it is today in device manufacturing. As devices became more integrated, cleanrooms became even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination. To prevent oxidation and to increase yield, FOUPs and semiconductor capital equipment may have a pure nitrogen environment with ISO class 1 levels of dust.

Wafers

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Processing

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.

Modern chips have up to eleven metal levels produced in over 300 sequenced processing steps.

Front-end-of-line (FEOL) processing

FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.

Gate oxide and implants

Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).

Back-end-of-line (BEOL) processing

Metal layers

Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.

Interconnect

Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green). Siliconchip by shapeshifter.png
Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green).

Historically, the metal wires have been composed of aluminum . In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique; this approach is still used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels is small (currently no more than four).

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-K insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three.

Wafer test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself. [1]

Device test

Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%. Process variation is one among many reasons for low yield. [25]

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to the predetermined test limits. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test".

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible, because many testers have the resources to perform most or all of the tests in parallel.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing, and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly-distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

Die preparation

Once tested, a wafer is typically reduced in thickness in a process also known as "backlap", [26] "backfinish" or "wafer thinning" [27] before the wafer is scored and then broken into individual dice, a process known as wafer dicing. Only the good, unmarked chips are packaged.

Packaging

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny wires are used to connect the pads to the pins. In the old days[ when? ], wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.

Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.

Hazardous materials

Many toxic materials are used in the fabrication process. [28] These include:

It is vital that workers should not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.

Timeline of MOSFET demonstrations

PMOS and NMOS

MOSFET (PMOS and NMOS) demonstrations
Date Channel length Oxide thickness [29] MOSFET logic Researcher(s)OrganizationRef
June 196025,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [14] [13] [30]
NMOS
20,000 nm100 nmPMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [31] [13] [30]
NMOS
October 196215,000 nm 120 nm PMOSFrederic P. Heiman, Steven R. Hofstein RCA Laboratories [32] [33]
February 1963 10,000 nm 100 nmPMOS Frank Wanlass, M. Papkoff, J. Kelly Fairchild Semiconductor [34]
May 196512,000 nm 150 nm PMOS Chih-Tang Sah, Otto Leistiko, A.S. GroveFairchild Semiconductor [35]
11,000 nm150 nmNMOS
8,000 nm
5,000 nm 170 nm PMOS
December 1972 1,000 nm ?PMOS Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu IBM T.J. Watson Research Center [36] [37] [38]
19737,500 nm?NMOSSohichi Suzuki NEC [39] [40]
6,000 nm ?PMOS? Toshiba [41] [42]
October 19741,000 nm 35 nm NMOS Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien YuIBM T.J. Watson Research Center [43]
500 nm
September 1975 1,500 nm 20 nm NMOSRyoichi Hori, Hiroo Masuda, Osamu Minato Hitachi [37] [44]
March 1976 3,000 nm ?NMOS? Intel [45]
April 19791,000 nm 25 nm NMOSWilliam R. Hunter, L. M. Ephrath, Alice CramerIBM T.J. Watson Research Center [46]
December 1984 100 nm 5 nm NMOSToshio Kobayashi, Seiji Horiguchi, K. KiuchiNippon Telegraph and Telephone [47]
December 1985 150 nm 2.5 nm NMOSToshio Kobayashi, Seiji Horiguchi, M. Miyake, M. OdaNippon Telegraph and Telephone [48]
75 nm ?NMOSStephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [49]
January 1986 60 nm ?NMOSStephen Y. Chou, Henry I. Smith, Dimitri A. AntoniadisMIT [50]
June 1987 200 nm 3.5 nm PMOSToshio Kobayashi, M. Miyake, K. DeguchiNippon Telegraph and Telephone [51]
December 1993 40 nm ?NMOSMizuki Ono, Masanobu Saito, Takashi YoshitomiToshiba [52]
September 1996 16 nm ?PMOSHisao Kawaura, Toshitsugu Sakamoto, Toshio BabaNEC [53]
June 1998 50 nm 1.3 nm NMOSKhaled Z. Ahmed, Effiong E. Ibok, Miryeong Song Advanced Micro Devices (AMD) [54] [55]
December 2002 6 nm ?PMOSBruce Doris, Omer Dokumaci, Meikei Ieong IBM [56] [57] [58]
December 2003 3 nm ?PMOSHitoshi Wakabayashi, Shigeharu YamagamiNEC [59] [57]
NMOS

CMOS (single-gate)

Complementary MOSFET (CMOS) demonstrations (single-gate)
Date Channel length Oxide thickness [29] Researcher(s)OrganizationRef
February 1963?? Chih-Tang Sah, Frank Wanlass Fairchild Semiconductor [15] [16]
196820,000 nm 100 nm ? RCA Laboratories [17]
1970 10,000 nm 100 nm?RCA Laboratories [17]
December 1976 2,000 nm ?A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White Mitel Semiconductor [60]
February 1978 3,000 nm ?Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai Hitachi Central Research Laboratory [61] [62] [63]
February 1983 1,200 nm 25 nm R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley Intel [64] [65]
900 nm 15 nm Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone (NTT) [64] [66]
December 1983 1,000 nm 22.5 nm G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting IBM T.J. Watson Research Center [67]
February 1987 800 nm 17 nm T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano Matsushita [64] [68]
700 nm 12 nm Tsuneo Mano, J. Yamada, Junichi Inoue, S. NakajimaNippon Telegraph and Telephone (NTT) [64] [69]
September 1987 500 nm 12.5 nm Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. HaddadIBM T.J. Watson Research Center [70]
December 1987 250 nm ?Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima NEC [71]
February 1988400 nm 10 nm M. Inoue, H. Kotani, T. Yamada, Hiroyuki YamauchiMatsushita [64] [72]
December 1990 100 nm ? Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. WarnockIBM T.J. Watson Research Center [73]
1993 350 nm ?? Sony [74]
1996 150 nm ?? Mitsubishi Electric
1998 180 nm ?? TSMC [75]
December 2003 5 nm ?Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki IkezawaNEC [59] [76]

Multi-gate MOSFET (MuGFET)

Multi-gate MOSFET (MuGFET) demonstrations
Date Channel length MuGFET typeResearcher(s)OrganizationRef
August 1984? DGMOS Toshihiro Sekigawa, Yutaka Hayashi Electrotechnical Laboratory (ETL) [77]
1987 2,000 nm DGMOSToshihiro SekigawaElectrotechnical Laboratory (ETL) [78]
December 1988 250 nm DGMOS Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh IBM T.J. Watson Research Center [79] [80]
180 nm
? GAAFET Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe Toshiba [81] [82] [83]
December 1989 200 nm FinFET Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda Hitachi Central Research Laboratory [84] [85] [86]
December 1998 17 nm FinFETDigh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor University of California (Berkeley) [87] [88]
2001 15 nm FinFET Chenming Hu, Yang‐Kyu Choi, Nick Lindert, Tsu-Jae King Liu University of California (Berkeley) [87] [89]
December 2002 10 nm FinFETShibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey BokorUniversity of California (Berkeley) [87] [90]
June 2006 3 nm GAAFETHyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu KAIST [91] [92]

Other types of MOSFET

MOSFET demonstrations (other types)
Date Channel length Oxide thickness [29] MOSFET type Researcher(s)OrganizationRef
October 1962?? TFT Paul K. Weimer RCA Laboratories [93] [94]
October 1966100,000 nm 100 nm TFTT.P. Brody, H.E. Kunig Westinghouse Electric [95] [96]
August 1967?? FGMOS Dawon Kahng, Simon Min Sze Bell Telephone Laboratories [97]
October 1967?? MNOS H.A. Richard Wegener, A.J. Lincoln, H.C. Pao Sperry Corporation [98]
July 1968?? BiMOS Hung-Chang Lin, Ramachandra R. Iyer Westinghouse Electric [99] [100]
October 1968?? BiCMOS Hung-Chang Lin, Ramachandra R. Iyer, C.T. HoWestinghouse Electric [101] [100]
1969?? VMOS ? Hitachi [102] [103]
September 1969?? DMOS Y. Tarui, Y. Hayashi, Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [104] [105]
October 1970?? ISFET Piet Bergveld University of Twente [106] [107]
October 1970 1,000 nm ?DMOSY. Tarui, Y. Hayashi, Toshihiro SekigawaElectrotechnical Laboratory (ETL) [108]
1977?? VDMOS John Louis Moll HP Labs [102]
?? LDMOS ?Hitachi [109]
July 1979?? IGBT Bantval Jayant Baliga, Margaret Lazeri General Electric [110]
December 1984 2,000 nm ?BiCMOSH. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. NishioHitachi [111]
May 1985 300 nm ??K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu Nippon Telegraph and Telephone [112]
February 1985 1,000 nm ?BiCMOSH. Momose, Hideki Shibata, S. Saitoh, Jun-ichi MiyamotoToshiba [113]
November 1986 90 nm 8.3 nm ?Han-Sheng Lee, L.C. Puzio General Motors [114]
December 1986 60 nm ?? Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith MIT [115] [50]
May 1987? 10 nm ? Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah IBM T.J. Watson Research Center [116]
December 1987 800 nm ?BiCMOSRobert H. Havemann, R. E. Eklund, Hiep V. Tran Texas Instruments [117]
June 1997 30 nm ?EJ-MOSFETHisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [118]
1998 32 nm ???NEC [57]
1999 8 nm
April 20008 nm?EJ-MOSFETHisao Kawaura, Toshitsugu Sakamoto, Toshio BabaNEC [119]

Timeline of commercial MOSFET nodes

See also

Related Research Articles

Moores law Heuristic law stating that the number of transistors on a integrated circuit doubles every two years

Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years. The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and CEO of Intel, whose 1965 paper described a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years, a compound annual growth rate (CAGR) of 41.4%.

N-type metal-oxide-semiconductor logic uses n-type MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off, triode, saturation, and velocity saturation.

SiGe, or silicon-germanium, is an alloy with any molar ratio of silicon and germanium, i.e. with a molecular formula of the form Si1−xGex. It is commonly used as a semiconductor material in integrated circuits (ICs) for heterojunction bipolar transistors or as a strain-inducing layer for CMOS transistors. IBM introduced the technology into mainstream manufacturing in 1989. This relatively new technology offers opportunities in mixed-signal circuit and analog circuit IC design and manufacture. SiGe is also used as a thermoelectric material for high temperature applications.

In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

The 90 nanometer (90 nm) process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

FinFET semiconductor manufacturing process

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS technology.

SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"siicon dioxide"—"silicon", is a cross sectional structure of MOSFET (metal-oxide-semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977. This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays. It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material. A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon"). Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia.

The 22 nanometer (22 nm) node is the process step following the 32 nm in MOSFET (CMOS) semiconductor device fabrication. The typical half-pitch for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012.

The 130 nanometer (130 nm) process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 2001-2002 timeframe, by leading semiconductor companies like Fujitsu, IBM, Intel, Texas Instruments, and TSMC.

Nanoelectronics refers to the use of nanotechnology in electronic components. The term covers a diverse set of devices and materials, with the common characteristic that they are so small that inter-atomic interactions and quantum mechanical properties need to be studied extensively. Some of these candidates include: hybrid molecular/semiconductor electronics, one-dimensional nanotubes/nanowires or advanced molecular electronics.

Multigate device type of MOS field-effect transistor with more than one gate

A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a MOSFET that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are the FinFET and the GAAFET, which are non-planar transistors, or 3D transistors.

Ghavam G. Shahidi is an Iranian-American electrical engineer and IBM Fellow. He is the director of Silicon Technology at the IBM Thomas J Watson Research Center. He is best known for his pioneering work in silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) technology since the late 1980s.

Nanocircuits are electrical circuits operating on the nanometer scale. This is well into the quantum realm, where quantum mechanical effects become very important. One nanometer is equal to 10−9 meters or a row of 10 hydrogen atoms. With such progressively smaller circuits, more can be fitted on a computer chip. This allows faster and more complex functions using less power. Nanocircuits are composed of three different fundamental components. These are transistors, interconnections, and architecture, all fabricated on the nanometer scale.

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nanometer (5 nm) node as the MOSFET technology node following the 7 nm node. As of 2019, Samsung Electronics and TSMC have begun commercial production of 5 nm nodes.

Bijan Davari is an Iranian-American engineer. He is an IBM Fellow and Vice President at IBM Thomas J Watson Research Center, Yorktown Hts, NY. His pioneering work in the miniaturization of semiconductor devices changed the world of computing. His research led to the first generation of voltage-scaled deep-submicron CMOS with sufficient performance to totally replace bipolar technology in IBM mainframes and enable new high-performance UNIX servers. He is credited with leading IBM into the use of copper and silicon on insulator before its rivals. He is a member of the U.S. National Academy of Engineers and is known for his seminal contributions to the field of CMOS technology. He is an IEEE Fellow, recipient of the J J Ebers Award in 2005 and IEEE Andrew S. Grove Award in 2010. At the present time, he leads the Next Generation Systems Area of research.

In semiconductor manufacturing, 3 nanometer, usually abbreviated 3 nm, is the next die shrink after the 5 nanometer MOSFET technology node. As of 2019, Samsung and TSMC have announced plans to put a 3nm semiconductor node into commercial production. It is based on GAAFET technology, a type of multi-gate MOSFET technology.

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