Wafer (electronics)

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Siliziumwafer.JPG ICC 2008 Poland Silicon Wafer 1 edit.png
Wafers on the conveyor (3347741252).jpg Solar World wafer (3347743800).jpg
  • Top: polished 12" and 6" silicon wafers. Their crystallographic orientation is marked by notches and flat cuts (left). VLSI microcircuits fabricated on a 12-inch (300 mm) silicon wafer, before dicing and packaging (right).
  • Bottom: solar wafers on the conveyor (left) and completed solar wafer (right)

In electronics, a wafer (also called a slice or substrate) [1] is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells. The wafer serves as the substrate for microelectronic devices built in and upon the wafer. It undergoes many microfabrication processes, such as doping, ion implantation, etching, thin-film deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and packaged as an integrated circuit.



In the 1950s, Mohamed Atalla investigated the surface properties of silicon semiconductors at Bell Labs, where he adopted a new method of semiconductor device fabrication, coating a silicon wafer with an insulating layer of silicon oxide, so that electricity could reliably penetrate to the conducting silicon below, overcoming the surface states that prevented electricity from reaching the semiconducting layer. This is known as surface passivation, a method that later became critical to the semiconductor industry as it made possible the mass-production of silicon integrated circuits (ICs). [2] [3] [4] The surface passivation method was presented by Atalla in 1957, [5] and was later the basis for the metal-oxide-semiconductor (MOS) process invented by Atalla and Dawon Kahng in 1959. [2]

By 1960, silicon wafers were being manufactured in the U.S. by companies such as MEMC/SunEdison. In 1965, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley, while working under IBM, filed Patent US3423629A [6] for the first high-capacity epitaxial apparatus.


The Czochralski process. Czochralski Process.svg
The Czochralski process.

Wafers are formed of highly pure, [7] nearly defect-free single crystalline material, with a purity of 99.9999999% (9N) or higher. [8] One process for forming crystalline wafers is known as Czochralski growth invented by the Polish chemist Jan Czochralski. In this process, a cylindrical ingot of high purity monocrystalline semiconductor, such as silicon or germanium, called a boule, is formed by pulling a seed crystal from a melt. [9] [10] Donor impurity atoms, such as boron or phosphorus in the case of silicon, can be added to the molten intrinsic material in precise amounts in order to dope the crystal, thus changing it into extrinsic semiconductor of n-type or p-type.

The boule is then sliced with a wafer saw (a type of wire saw) and polished to form wafers. [11] The size of wafers for photovoltaics is 100–200 mm square and the thickness is 100–500 μm. [12] Electronics use wafer sizes from 100–450 mm diameter. The largest wafers made have a diameter of 450 mm [13] but are not yet in general use.

Cleaning, texturing and etching

Wafers are cleaned with weak acids to remove unwanted particles, or repair damage caused during the sawing process. When used for solar cells, the wafers are textured to create a rough surface to increase their efficiency. The generated PSG (phosphosilicate glass) is removed from the edge of the wafer in the etching. [14]

Wafer properties

Standard wafer sizes

Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches). [15] [16] Semiconductor fabrication plants, colloquially known as fabs, are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using 300 mm, with a proposal to adopt 450 mm. [17] [18] Intel, TSMC and Samsung are separately conducting research to the advent of 450 mm "prototype" (research) fabs, though serious hurdles remain.

2-inch (51 mm), 4-inch (100 mm), 6-inch (150 mm), and 8-inch (200 mm) wafers Wafer 2 Zoll bis 8 Zoll 2.jpg
2-inch (51 mm), 4-inch (100 mm), 6-inch (150 mm), and 8-inch (200 mm) wafers
Wafer sizeThicknessYear Prodn [15] Weight per wafer100 mm2 (10 mm) Die per wafer
1-inch (25 mm)1960
2-inch (51 mm)275 μm 1969
3-inch (76 mm)375 μm1972
4-inch (100 mm)525 μm197610 grams [19] 56
4.9 inch (125 mm)625 μm1981
150  mm (5.9 inch, usually referred to as "6 inch")675 μm1983
200 mm (7.9 inch, usually referred to as "8 inch")725 μm.199253 grams [19] 269
300 mm (11.8 inch, usually referred to as "12 inch")775 μm2002125 grams [19] 640
450 mm (17.7 inch)(proposed). [20] 925 μmfuture342 grams [19] 1490
675-millimetre (26.6 in) (Theoretical). [21] Unknown.future

Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The weight of the wafer goes up along thickness and diameter.

Historical increases of wafer size

A unit wafer fabrication step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from 200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%. [22] Larger diameter wafers allow for more die per wafer:

Proposed 450 mm transition

There is considerable resistance to the 450 mm transition despite the possible productivity improvement, because of concern about insufficient return on investment. [22] There are also issues related to increased inter-die / edge-to-edge wafer variation and additional edge defects. 450mm wafers are expected to cost 4 times as much as 300mm wafers, and equipment costs are expected to rise by 20 to 50%. [23] Higher cost semiconductor fabrication equipment for larger wafers increases the cost of 450 mm fabs (semiconductor fabrication facilities or factories). Lithographer Chris Mack claimed in 2012 that the overall price per die for 450 mm wafers would be reduced by only 10–20% compared to 300 mm wafers, because over 50% of total wafer processing costs are lithography-related. Converting to larger 450 mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count, not wafer area. Cost for processes such as lithography is proportional to wafer area, and larger wafers would not reduce the lithography contribution to die cost. [24] Nikon planned to deliver 450-mm lithography equipment in 2015, with volume production in 2017. [25] [26] In November 2013 ASML paused development of 450-mm lithography equipment, citing uncertain timing of chipmaker demand. [27]

The timeline for 450 mm has not been fixed. In 2012, it was expected that 450mm production would start in 2017, which never realized. [28] [29] Mark Durcan, then CEO of Micron Technology, said in February 2014 that he expects 450 mm adoption to be delayed indefinitely or discontinued. "I am not convinced that 450mm will ever happen but, to the extent that it does, it’s a long way out in the future. There is not a lot of necessity for Micron, at least over the next five years, to be spending a lot of money on 450mm. There is a lot of investment that needs to go on in the equipment community to make that happen. And the value at the end of the day – so that customers would buy that equipment – I think is dubious." [30] As of March 2014, Intel Corporation expected 450 mm deployment by 2020 (by the end of this decade). [31] Mark LaPedus of semiengineering.com reported in mid-2014 that chipmakers had delayed adoption of 450 mm "for the foreseeable future." According to this report some observers expected 2018 to 2020, while G. Dan Hutcheson, chief executive of VLSI Research, didn't see 450mm fabs moving into production until 2020 to 2025. [32]

The step up to 300 mm required major changes, with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers, partly because a FOUP for 300 mm wafers weighs about 7.5 kilograms [33] when loaded with 25 300 mm wafers where a SMIF weighs about 4.8 kilograms [34] [35] [19] when loaded with 25 200 mm wafers, thus requiring twice the amount of physical strength from factory workers, and increasing fatigue. 300mm FOUPs have handles so that they can be still be moved by hand. 450mm FOUPs weigh 45 kilograms [36] when loaded with 25 450 mm wafers, thus cranes are necessary to manually handle the FOUPs [37] and handles are no longer present in the FOUP. FOUPs are moved around using material handling systems from Muratec or Daifuku. These major investments were undertaken in the economic downturn following the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe. On the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2–4 times longer to cool, and the process time will be double. [38] All told, the development of 450 mm wafers requires significant engineering, time, and cost to overcome.

Analytical die count estimation

In order to minimize the cost per die, manufacturers wish to maximize the number of dies that can be made from a single wafer; dies always have a square or rectangular shape due to the constraint of wafer dicing. In general, this is a computationally complex problem with no analytical solution, dependent on both the area of the dies as well as their aspect ratio (square or rectangular) and other considerations such as scribeline size and the space occupied by alignment and test structures. Note that gross DPW formulas account only for wafer area that is lost because it cannot be used to make physically complete dies; gross DPW calculations do not account for yield loss due to defects or parametric issues.

Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer. Wafermap showing fully and partially patterned dies.svg
Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer.

Nevertheless, the number of gross die per wafer (DPW) can be estimated starting with the first-order approximation or wafer-to-die area ratio,


where is the wafer diameter (typically in mm) and the size of each die (mm2). This formula simply states that the number of dies which can fit on the wafer cannot exceed the area of the wafer divided by the area of each individual die. It will always overestimate the true best-case gross DPW, since it includes the area of partially patterned dies which do not fully lie on the wafer surface (see figure). These partially patterned dies don't represent complete ICs, so they cannot be sold as functional parts.

Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible.

The correction factor or correction term generally takes one of the forms cited by De Vries: [39]

(area ratio - circumference/(die diagonal length))
or (area ratio scaled by an exponential factor)
or (area ratio scaled by a polynomial factor).

Studies comparing these analytical formulas to brute-force computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension with (average side length) in the case of dies with large aspect ratio: [39]

or .

Crystalline orientation

Diamond cubic crystal structure of a silicon unit cell Silicon-unit-cell-3D-balls.png
Diamond cubic crystal structure of a silicon unit cell
Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed. Wafer flats convention v2.svg
Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed.

Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm). [40] When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with (100) or (111) faces being the most common for silicon. [40] Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport. [41] Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

Crystallographic orientation notches

Wafers under 200 mm diameter have flats cut into one or more sides indicating the crystallographic planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200 mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type. [42]

Impurity doping

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 1013 and 1016 atoms per cm3 of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type. [43] However, compared with single-crystal silicon's atomic density of 5×1022 atoms per cm3, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum. [44] Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications. [45]

Compound semiconductors

While silicon is the prevalent material for wafers used in the electronics industry, other compound III-V or II-VI materials have also been employed. Gallium arsenide (GaAs), a III-V semiconductor produced via the Czochralski process, Gallium nitride (GaN) and Silicon carbide (SiC), are also common wafer materials, with GaN and Sapphire being extensively used in LED manufacturing. [10]

See also

Related Research Articles

Photolithography, also called optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a photosensitive chemical photoresist on the substrate. A series of chemical treatments then either etches the exposure pattern into the material or enables deposition of a new material in the desired pattern upon the material underneath the photoresist. In complex integrated circuits, a CMOS wafer may go through the photolithographic cycle as many as 50 times.

Semiconductor device fabrication manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal-oxide-semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

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Czochralski process Method of crystal growth

The Czochralski process is a method of crystal growth used to obtain single crystals of semiconductors, metals, salts and synthetic gemstones. The process is named after Polish scientist Jan Czochralski, who invented the method in 1915 while investigating the crystallization rates of metals. He made this discovery by accident: instead of dipping his pen into his inkwell, he dipped it in molten tin, and drew a tin filament, which later proved to be a single crystal.

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SMIF (interface)

SMIF is an isolation technology developed in the 1980s by a group known as the "micronauts" at Hewlett-Packard in Palo Alto. The system is used in semiconductor wafer fabrication and cleanroom environments. It is a SEMI standard.

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Thermal oxidation process creating a thin layer of silicon dioxide

In microfabrication, thermal oxidation is a way to produce a thin layer of oxide on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The rate of oxide growth is often predicted by the Deal–Grove model. Thermal oxidation may be applied to different materials, but most commonly involves the oxidation of silicon substrates to produce silicon dioxide.

The Deal–Grove model mathematically describes the growth of an oxide layer on the surface of a material. In particular, it is used to predict and interpret thermal oxidation of silicon in semiconductor device fabrication. The model was first published in 1965 by Bruce Deal and Andrew Grove, of Fairchild Semiconductor, and served as an step in the development of CMOS devices and the fabrication of integrated circuits.

Etching (microfabrication) technique in microfabrication

Etching is used in microfabrication to chemically remove layers from the surface of a wafer during manufacturing. Etching is a critically important process module, and every wafer undergoes many etching steps before it is complete.

Direct and indirect band gaps Types of band gaps

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Tower Semiconductor Ltd. (TowerJazz), and its fully owned U.S. subsidiaries Jazz Semiconductor and TowerJazz Texas, operate collectively under the brand name TowerJazz. TowerJazz manufactures integrated circuits offering a range of customizable analog specialty process technologies, including SiGe, BiCMOS, SOI, mixed-signal and RFCMOS, CMOS image sensors, power management (BCD), and non-volatile memory (NVM) as well as MEMS capabilities. TowerJazz also owns 51% of TowerJazz Panasonic Semiconductor Co. (TPSCo), an enterprise with Panasonic Corporation.


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