Wafer (electronics)

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Siliziumwafer.JPG ICC 2008 Poland Silicon Wafer 1 edit.png
Wafers on the conveyor (3347741252).jpg Solar World wafer (3347743800).jpg
  • Top: polished 12" and 6" silicon wafers. Their crystallographic orientation is marked by notches and flat cuts (left). VLSI microcircuits fabricated on a 12-inch (300 mm) silicon wafer, before dicing and packaging (right).
  • Bottom: solar wafers on the conveyor (left) and completed solar wafer (right)

In electronics, a wafer (also called a slice or substrate) [1] is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells. The wafer serves as the substrate for microelectronic devices built in and upon the wafer. It undergoes many microfabrication processes, such as doping, ion implantation, etching, thin-film deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and packaged as an integrated circuit.

Electronics physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter

Electronics comprises the physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter.

A semiconductor material has an electrical conductivity value falling between that of a conductor, such as metallic copper, and an insulator, such as glass. Its resistance decreases as its temperature increases, which is behaviour opposite to that of a metal. Its conducting properties may be altered in useful ways by the deliberate, controlled introduction of impurities ("doping") into the crystal structure. Where two differently-doped regions exist in the same crystal, a semiconductor junction is created. The behavior of charge carriers which include electrons, ions and electron holes at these junctions is the basis of diodes, transistors and all modern electronics. Some examples of semiconductors are silicon, germanium, gallium arsenide, and elements near the so-called "metalloid staircase" on the periodic table. After silicon, gallium arsenide is the second most common semiconductor and is used in laser diodes, solar cells, microwave-frequency integrated circuits and others. Silicon is a critical element for fabricating most electronic circuits.

Crystalline silicon

Crystalline silicon (c-Si) is the crystalline forms of silicon, either multicrystalline silicon (multi-Si) consisting of small crystals, or monocrystalline silicon (mono-Si), a continuous crystal. Crystalline silicon is the dominant semiconducting material used in photovoltaic technology for the production of solar cells. These cells are assembled into solar panels as part of a photovoltaic system to generate solar power from sunlight.

Contents

History

By 1960, silicon wafers were being manufactured in the U.S. by companies such as MEMC/SunEdison. In 1965, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley, while working under IBM, filed Patent US3423629A [2] for the first high-capacity epitaxial apparatus.

SunEdison, Inc. is a renewable energy company headquartered in the U.S. In addition to developing, building, owning, and operating solar power plants and wind energy plants, it also manufactures high purity polysilicon, monocrystalline silicon ingots, silicon wafers, solar modules, solar energy systems, and solar module racking systems. Originally a silicon-wafer manufacturer established in 1959 as the Monsanto Electronic Materials Company, Monsanto sold the company in 1989.

IBM American multinational technology and consulting corporation

International Business Machines Corporation (IBM) is an American multinational information technology company headquartered in Armonk, New York, with operations in over 170 countries. The company began in 1911, founded in Endicott, New York, as the Computing-Tabulating-Recording Company (CTR) and was renamed "International Business Machines" in 1924.

Epitaxy crystal growth process

Epitaxy refers to the deposition of a crystalline overlayer on a crystalline substrate.

Formation

The Czochralski process. Czochralski Process.svg
The Czochralski process.

Wafers are formed of highly pure (99.9999999% purity), [3] nearly defect-free single crystalline material. [4] One process for forming crystalline wafers is known as Czochralski growth invented by the Polish chemist Jan Czochralski. In this process, a cylindrical ingot of high purity monocrystalline semiconductor, such as silicon or germanium, called a boule, is formed by pulling a seed crystal from a melt. [5] [6] Donor impurity atoms, such as boron or phosphorus in the case of silicon, can be added to the molten intrinsic material in precise amounts in order to dope the crystal, thus changing it into extrinsic semiconductor of n-type or p-type.

Czochralski process Method of crystal growth

The Czochralski process is a method of crystal growth used to obtain single crystals of semiconductors, metals, salts and synthetic gemstones. The process is named after Polish scientist Jan Czochralski, who invented the method in 1915 while investigating the crystallization rates of metals. He made this discovery by accident, while studying the crystallization rate of metals: instead of dipping his pen into his inkwell, he dipped it in molten tin, and drew a tin filament, which later proved to be a single crystal.

Jan Czochralski Polish chemist and engineer

Jan Czochralski was a Polish chemist who invented the Czochralski process, which is used for growing single crystals and in the production of semiconductor wafers. He is the most cited Polish scholar. He was also known for extraordinary physical strength.

Ingot material, usually metal, that is cast into a shape suitable for further processing

An ingot is a piece of relatively pure material, usually metal, that is cast into a shape suitable for further processing. In steelmaking, it is the first step among semi-finished casting products. Ingots usually require a second procedure of shaping, such as cold/hot working, cutting, or milling to produce a useful final product. Non-metallic and semiconductor materials prepared in bulk form may also be referred to as ingots, particularly when cast by mold based methods. Precious metal ingots can be used as currency, or as a currency reserve, as with gold bars.

The boule is then sliced with a wafer saw (a type of wire saw) and polished to form wafers. [7] The size of wafers for photovoltaics is 100–200 mm square and the thickness is 100–500 μm. "Silicon Solar Cell Parameters" . Retrieved 2019-06-27.</ref> Electronics use wafer sizes from 100–450 mm diameter. The largest wafers made have a diameter of 450 mm [8] but are not yet in general use.

Wire saw saw

A wire saw is a saw that uses a metal wire or cable for cutting. Industrial wire saws are usually powered. There are also hand-powered survivalist wire saws suitable for cutting branches. Wire saws are classified as continuous or oscillating. Sometimes the wire itself is referred to as a "blade".

Polishing is the process of creating a smooth and shiny surface by rubbing it or using a chemical action, leaving a surface with a significant specular reflection In some materials, polishing is also able to reduce diffuse reflection to minimal values. When an unpolished surface is magnified thousands of times, it usually looks like mountains and valleys. By repeated abrasion, those "mountains" are worn down until they are flat or just small "hills." The process of polishing with abrasives starts with coarse ones and graduates to fine ones.

Cleaning, texturing and etching

Wafers are cleaned with weak acids to remove unwanted particles, or repair damage caused during the sawing process. When used for solar cells, the wafers are textured to create a rough surface to increase their efficiency. The generated PSG (phosphosilicate glass) is removed from the edge of the wafer in the etching. [9]

Solar cell electrical device that converts the energy of light directly into electricity by the photovoltaic effect

A solar cell, or photovoltaic cell, is an electrical device that converts the energy of light directly into electricity by the photovoltaic effect, which is a physical and chemical phenomenon. It is a form of photoelectric cell, defined as a device whose electrical characteristics, such as current, voltage, or resistance, vary when exposed to light. Individual solar cell devices can be combined to form modules, otherwise known as solar panels. In basic terms a single junction silicon solar cell can produce a maximum open-circuit voltage of approximately 0.5 to 0.6 volts.

Phosphosilicate glass, commonly referred to by the acronym PSG, is a silicate glass commonly used in semiconductor device fabrication for intermetal layers, i.e., insulating layers deposited between succeedingly higher metal or conducting layers, due to its effect in gettering alkali ions. Another common species of phosphosilicate glass is borophosphosilicate glass (BPSG).

Etching intaglio printmaking technique

Etching is traditionally the process of using strong acid or mordant to cut into the unprotected parts of a metal surface to create a design in intaglio (incised) in the metal. In modern manufacturing, other chemicals may be used on other types of material. As a method of printmaking, it is, along with engraving, the most important technique for old master prints, and remains in wide use today. In a number of modern variants such as microfabrication etching and photochemical milling it is a crucial technique in much modern technology, including circuit boards.

Wafer properties

Standard wafer sizes

Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches). [10] [11] Semiconductor fabrication plants, colloquially known as fabs, are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using 300 mm, with a proposal to adopt 450 mm. [12] [13] Intel, TSMC and Samsung are separately conducting research to the advent of 450 mm "prototype" (research) fabs, though serious hurdles remain.

In the microelectronics industry, a semiconductor fabrication plant is a factory where devices such as integrated circuits are manufactured.

Intel American semiconductor company

Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley. It is the world's second largest and second highest valued semiconductor chip manufacturer based on revenue after being overtaken by Samsung Electronics, and is the inventor of the x86 series of microprocessors, the processors found in most personal computers (PCs). Intel ranked No. 46 in the 2018 Fortune 500 list of the largest United States corporations by total revenue.

TSMC semiconductor foundry company

Taiwan Semiconductor Manufacturing Company, Limited, also known as Taiwan Semiconductor, is the world's largest dedicated independent (pure-play) semiconductor foundry, with its headquarters and main operations located in the Hsinchu Science and Industrial Park in Hsinchu, Taiwan.

2-inch (51 mm), 4-inch (100 mm), 6-inch (150 mm), and 8-inch (200 mm) wafers Wafer 2 Zoll bis 8 Zoll 2.jpg
2-inch (51 mm), 4-inch (100 mm), 6-inch (150 mm), and 8-inch (200 mm) wafers
Wafer sizeThicknessWeight per wafer100 mm2 (10 mm) Die per wafer
1-inch (25 mm)
2-inch (51 mm)275 µm
3-inch (76 mm)375 µm
4-inch (100 mm)525 µm10 grams [14] 56
4.9 inch (125 mm)625 µm
150  mm (5.9 inch, usually referred to as "6 inch")675 µm
200 mm (7.9 inch, usually referred to as "8 inch")725 µm.53 grams [14] 269
300 mm (11.8 inch, usually referred to as "12 inch")775 µm125 grams [14] 640
450 mm (17.7 inch)(proposed). [15] 925 µm342 grams [14] 1490
675-millimetre (26.6 in) (Theoretical). [16] Unknown thickness.

Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The weight of the wafer goes up along thickness and diameter.

Historical increases of wafer size

A unit wafer fabrication step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from 200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%. [17] Larger diameter wafers allow for more die per wafer:

Proposed 450 mm transition

There is considerable resistance to the 450 mm transition despite the possible productivity improvement, because of concern about insufficient return on investment. [17] Higher cost semiconductor fabrication equipment for larger wafers increases the cost of 450 mm fabs (semiconductor fabrication facilities or factories). Lithographer Chris Mack claimed in 2012 that the overall price per die for 450 mm wafers would be reduced by only 10–20% compared to 300 mm wafers, because over 50% of total wafer processing costs are lithography-related. Converting to larger 450 mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count, not wafer area. Cost for processes such as lithography is proportional to wafer area, and larger wafers would not reduce the lithography contribution to die cost. [18] Nikon planned to deliver 450-mm lithography equipment in 2015, with volume production in 2017. [19] [20] In November 2013 ASML paused development of 450-mm lithography equipment, citing uncertain timing of chipmaker demand. [21]

The timeline for 450 mm has not been fixed. Mark Durcan, then CEO of Micron Technology, said in February 2014 that he expects 450 mm adoption to be delayed indefinitely or discontinued. “I am not convinced that 450mm will ever happen but, to the extent that it does, it’s a long way out in the future. There is not a lot of necessity for Micron, at least over the next five years, to be spending a lot of money on 450mm. There is a lot of investment that needs to go on in the equipment community to make that happen. And the value at the end of the day – so that customers would buy that equipment – I think is dubious.” [22] As of March 2014, Intel Corporation expected 450 mm deployment by 2020 (by the end of this decade). [23] Mark LaPedus of semiengineering.com reported in mid-2014 that chipmakers had delayed adoption of 450 mm “for the foreseeable future.” According to this report some observers expected 2018 to 2020, while G. Dan Hutcheson, chief executive of VLSI Research, didn’t see 450mm fabs moving into production until 2020 to 2025. [24]

The step up to 300 mm required major changes, with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers, partly because a FOUP for 300 mm wafers weighs about 7.5 kilograms [25] when loaded with 25 300 mm wafers where a SMIF weighs about 4.8 kilograms [26] [27] [14] when loaded with 25 200 mm wafers, thus requiring twice the amount of physical strength from factory workers, and increasing fatigue. 300mm FOUPs have handles so that they can be still be moved by hand. 450mm FOUPs weigh 45 kilograms [28] when loaded with 25 450 mm wafers, thus cranes are necessary to handle the FOUPs [29] and handles are no longer present in the FOUP. FOUPs are moved around using material handling systems from Muratec or Daifuku. These major investments were undertaken in the economic downturn following the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe. On the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2–4 times longer to cool, and the process time will be double. [30] All told, the development of 450 mm wafers requires significant engineering, time, and cost to overcome.

Analytical die count estimation

In order to minimize the cost per die, manufacturers wish to maximize the number of dies that can be made from a single wafer; dies always have a square or rectangular shape due to the constraint of wafer dicing. In general, this is a computationally complex problem with no analytical solution, dependent on both the area of the dies as well as their aspect ratio (square or rectangular) and other considerations such as scribeline size and the space occupied by alignment and test structures. Note that gross DPW formulas account only for wafer area that is lost because it cannot be used to make physically complete dies; gross DPW calculations do not account for yield loss due to defects or parametric issues.

Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer. Wafermap showing fully and partially patterned dies.svg
Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer.

Nevertheless, the number of gross die per wafer (DPW) can be estimated starting with the first-order approximation or wafer-to-die area ratio,

,

where is the wafer diameter (typically in mm) and the size of each die (mm2). This formula simply states that the number of dies which can fit on the wafer cannot exceed the area of the wafer divided by the area of each individual die. It will always overestimate the true best-case gross DPW, since it includes the area of partially patterned dies which do not fully lie on the wafer surface (see figure). These partially patterned dies don't represent complete ICs, so they cannot be sold as functional parts.

Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible.

The correction factor or correction term generally takes one of the forms cited by De Vries: [31]

(area ratio - circumference/(die diagonal length))
or (area ratio scaled by an exponential factor)
or (area ratio scaled by a polynomial factor).

Studies comparing these analytical formulas to brute-force computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension with (average side length) in the case of dies with large aspect ratio: [31]

or
or .

Crystalline orientation

Diamond cubic crystal structure of a silicon unit cell Silicon-unit-cell-3D-balls.png
Diamond cubic crystal structure of a silicon unit cell
Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed. Wafer flats convention v2.svg
Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed.

Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm). [32] When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with (100) or (111) faces being the most common for silicon. [32] Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport. [33] Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

Crystallographic orientation notches

Wafers under 200 mm diameter have flats cut into one or more sides indicating the crystallographic planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200 mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type. [34]

Impurity doping

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 1013 and 1016 atoms per cm3 of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type. [35] However, compared with single-crystal silicon's atomic density of 5×1022 atoms per cm3, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum. [36] Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications. [37]

Compound semiconductors

While silicon is the prevalent material for wafers used in the electronics industry, other compound III-V or II-VI materials have also been employed. Gallium arsenide (GaAs), a III-V semiconductor produced via the Czochralski process, Gallium nitride (GaN) and Silicon carbide (SiC), are also common wafer materials, with GaN and Sapphire being extensively used in LED manufacturing. [6]

See also

Related Research Articles

Photolithography, also called optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a photosensitive chemical photoresist on the substrate. A series of chemical treatments then either etches the exposure pattern into the material or enables deposition of a new material in the desired pattern upon the material underneath the photoresist. In complex integrated circuits, a CMOS wafer may go through the photolithographic cycle as many as 50 times.

Semiconductor device fabrication process used to create the integrated circuits that are present in everyday electrical and electronic devices

Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Rectifier AC-DC conversion device; electrical device that converts alternating current (AC), which periodically reverses direction, to direct current (DC), which flows in only one direction

A rectifier is an electrical device that converts alternating current (AC), which periodically reverses direction, to direct current (DC), which flows in only one direction.

In solid state physics, a particle's effective mass is the mass that it seems to have when responding to forces, or the mass that it seems to have when interacting with other identical particles in a thermal distribution. One of the results from the band theory of solids is that the movement of particles in a periodic potential, over long distances larger than the lattice spacing, can be very different from their motion in a vacuum. The effective mass is a quantity that is used to simplify band structures by modeling the behavior of a free particle with that mass. For some purposes and some materials, the effective mass can be considered to be a simple constant of a material. In general, however, the value of effective mass depends on the purpose for which it is used, and can vary depending on a number of factors.

Effusion process of a gas escaping through a small hole

In physics and chemistry, effusion is the process in which a gas escapes from a container through a hole of diameter considerably smaller than the mean free path of the molecules. Such a hole is often described as a pinhole and the escape of the gas is due to the pressure difference between the container and the exterior. Under these conditions, essentially all molecules which arrive at the hole continue and pass through the hole, since collisions between molecules in the region of the hole are negligible. Conversely, when the diameter is larger than the mean free path of the gas, flow obeys the Sampson flow law.

Planar process

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor, with a first patent issued 1959.

SMIF (interface)

SMIF is an isolation technology developed in the 1980s by a group known as the "micronauts" at Hewlett-Packard in Palo Alto. The system is used in semiconductor wafer fabrication and cleanroom environments. It is a SEMI standard.

Stepper

A stepper is a device used in the manufacture of integrated circuits (ICs) that is similar in operation to a slide projector or a photographic enlarger. The term "stepper" is short for step-and-repeat camera. Steppers are an essential part of the complex process, called photolithography, that creates millions of microscopic circuit elements on the surface of tiny chips of silicon. These chips form the heart of ICs such as computer processors, memory chips, and many other devices.

In optics, an index ellipsoid is a diagram of an ellipsoid that depicts the orientation and relative magnitude of refractive indices in a crystal .

ASML is a Dutch company and currently the largest supplier in the world of photolithography systems for the semiconductor industry. The company manufactures machines for the production of integrated circuits. The company is a component of the Euro Stoxx 50 stock market index.

Surface states are electronic states found at the surface of materials. They are formed due to the sharp transition from solid material that ends with a surface and are found only at the atom layers closest to the surface. The termination of a material with a surface leads to a change of the electronic band structure from the bulk material to the vacuum. In the weakened potential at the surface, new electronic states can be formed, so called surface states.

In crystallography, atomic packing factor (APF), packing efficiency or packing fraction is the fraction of volume in a crystal structure that is occupied by constituent particles. It is a dimensionless quantity and always less than unity. In atomic systems, by convention, the APF is determined by assuming that atoms are rigid spheres. The radius of the spheres is taken to be the maximum value such that the atoms do not overlap. For one-component crystals, the packing fraction is represented mathematically by

The piezoresistive effect is a change in the electrical resistivity of a semiconductor or metal when mechanical strain is applied. In contrast to the piezoelectric effect, the piezoresistive effect causes a change only in electrical resistance, not in electric potential.

FOUP is an acronym for Front Opening Unified Pod or Front Opening Universal Pod.

Thermal oxidation process creating a thin layer of silicon dioxide

In microfabrication, thermal oxidation is a way to produce a thin layer of oxide on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. Research into thermal oxidation was pioneered for the fabrication of Metal–oxide–semiconductors at Fairchild Semiconductor which led to the development of technologies that enable the fabrication of integrated circuits. The rate of oxide growth is often predicted by the Deal–Grove model. Thermal oxidation may be applied to different materials, but most commonly involves the oxidation of silicon substrates to produce silicon dioxide.

Etching (microfabrication) technique in microfabrication

Etching is used in microfabrication to chemically remove layers from the surface of a wafer during manufacturing. Etching is a critically important process module, and every wafer undergoes many etching steps before it is complete.

GlobalFoundries is an American semiconductor foundry headquartered in Santa Clara, California, United States. GlobalFoundries was created by the divestiture of the manufacturing arm of Advanced Micro Devices (AMD) on March 2, 2009, expanded through the acquisition of Chartered Semiconductor on January 23, 2010, and further expanded through the acquisition of IBM Microelectronics on July 1, 2015. The Emirate of Abu Dhabi is the owner of the company through its subsidiary Advanced Technology Investment Company (ATIC). On March 4, 2012, AMD announced they divested their final 14% stake in the company, which concluded AMD's multi-year plan to divest its manufacturing arm.

Klaibers law

Simply stated, Klaiber's law proposes that "the silicon wafer size will dictate the largest diameter of ultrapure water supply piping needed within a semiconductor wafer factory."

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