Wafer testing

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Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.

Die preparation

Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation typically consists of two steps: wafer mounting and wafer dicing.

ATPG is an electronic design automation method/technology used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure. The effectiveness of ATPG is measured by the number of modeled defects, or fault models, detectable and by the number of generated patterns. These metrics generally indicate test quality and test application time. ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test, the level of abstraction used to represent the circuit under test, and the required test quality.

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Wafer prober

8-inch semiconductor wafer prober, shown with cover panels, tester and probe card elements removed. Wafer prober service configuration.jpg
8-inch semiconductor wafer prober, shown with cover panels, tester and probe card elements removed.

A wafer prober is a machine (Automatic test equipment) used to test integrated circuits. For electrical testing a set of microscopic contacts or probes called a probe card are held in place whilst the wafer, vacuum-mounted on a wafer chuck, is moved into electrical contact. When a die (or array of dice) have been electrically tested the prober moves the wafer to the next die (or array) and the next test can start. The wafer prober is usually responsible for loading and unloading the wafers from their carrier (or cassette) and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the contact pads on the wafer and the tips of the probes.

Automatic test equipment apparatus used in Hardware testing

Automatic test equipment or automated test equipment (ATE) is any apparatus that performs tests on a device, known as the device under test (DUT), equipment under test (EUT) or unit under test (UUT), using automation to quickly perform measurements and evaluate the test results. An ATE can be a simple computer-controlled digital multimeter, or a complicated system containing dozens of complex test instruments capable of automatically testing and diagnosing faults in sophisticated electronic packaged parts or on wafer testing, including system on chips and integrated circuits.

Probe card

A probe card is an interface between an electronic test system and a semiconductor wafer. Typically the probe card is mechanically docked to a prober and electrically connected to a tester. Its purpose is to provide an electrical path between the test system and the circuits on the wafer, thereby permitting the testing and validation of the circuits at the wafer level, usually before they are diced and packaged. It consists, normally, of a printed circuit board (PCB) and some form of contact elements, usually metallic, but possibly of other materials as well.

Contact pad

Contact pads or bond pads are designated surface areas of a printed circuit board or die of an integrated circuit. Possibilities to contact to pads include soldering, wirebonding, flip chip mounting, or probe needles.

For today's multi-die packages such as stacked chip-scale package (SCSP) or system in package (SiP) – the development of non-contact (RF) probes for identification of known tested die (KTD) and known good die (KGD) are critical to increasing overall system yield.

Chip-scale package

A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.

The wafer prober also exercises any test circuitry on the wafer scribe lines. Some companies get most of their information about device performance from these scribe line test structures. [1] [2] [3]

When all test patterns pass for a specific die, its position is remembered for later use during IC packaging. Sometimes a die has internal spare resources available for repairing (i.e. flash memory IC); if it does not pass some test patterns these spare resources can be used. If redundancy of failed die is not possible the die is considered faulty and is discarded. Non-passing circuits are typically marked with a small dot of ink in the middle of the die, or the information of passing/non-passing is stored in a file, named a wafermap. This map categorizes the passing and non-passing dies by making use of bins. A bin is then defined as a good or bad die. This wafermap is then sent to the die attachment process which then only picks up the passing circuits by selecting the bin number of good dies. The process where no ink dot is used to mark the bad dies is named substrate mapping. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot.

Integrated circuit packaging Final stage of semiconductor device fabrication

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

Substrate mapping is a process in which the performance of semiconductor devices on a substrate is represented by a map showing the performance as a colour-coded grid. The map is a convenient representation of the variation in performance across the substrate, since the distribution of those variations may be a clue as to their cause.

In some very specific cases, a die that passes some but not all test patterns can still be used as a product, typically with limited functionality. The most common example of this is a microprocessor for which only one part of the on-die cache memory is functional. In this case, the processor can sometimes still be sold as a lower cost part with a smaller amount of memory and thus lower performance. Additionally when bad dies have been identified, the die from the bad bin can be used by production personnel for assembly line setup.

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost to access data from the main memory. A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of more cache levels.

The contents of all test patterns and the sequence by which they are applied to an integrated circuit are called the test program.

After IC packaging, a packaged chip will be tested again during the IC testing phase, usually with the same or very similar test patterns. For this reason, it may be thought that wafer testing is an unnecessary, redundant step. In reality this is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when the production yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and dies will undergo blind assembly.

See also

Related Research Articles

Semiconductor device fabrication manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to create the MOSFET semiconductor devices used in the integrated circuits (ICs) that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Dual in-line package Type of electronic component package

In microelectronics, a dual in-line package, or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits. Increasingly complex circuits required more signal and power supply leads ; eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density chip carriers. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.

Stepper

A stepper is a device used in the manufacture of integrated circuits (ICs) that is similar in operation to a slide projector or a photographic enlarger. The term "stepper" is short for step-and-repeat camera. Steppers are an essential part of the complex process, called photolithography, that creates millions of microscopic circuit elements on the surface of tiny chips of silicon. These chips form the heart of ICs such as computer processors, memory chips, and many other devices.

Back end of line

The back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring on the wafer, the metalization layer. Common metals are copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

Integrated circuit design Engineering process for electronic hardware

Integrated circuit design, or IC design, is a subset of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

A device under test (DUT), also known as equipment under test (EUT) and unit under test (UUT), is a manufactured product undergoing testing, either at first manufacture or later during its life cycle as part of ongoing functional testing and calibration checks. This can include a test after repair to establish that the product is performing in accordance with the original product specification.

Package on package (PoP) is an integrated circuit packaging method to combine vertically discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras.

Through-silicon via

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits, in microelectronics and nanoelectronics.

Non contact wafer testing is a normal step in semiconductor device fabrication, used to detect defects in integrated circuits (IC) before they are assembled during the IC packaging step.

Wafer-level packaging

Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment.

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting the package to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

Tokyo Electron Japanese company

Tokyo Electron Limited, or TEL, is a Japanese electronics and semiconductor company headquartered in Akasaka, Minato-ku, Tokyo, Japan.

Rudolph Technologies, Inc. is an American semiconductor company. Formed in 1940 and traded as NYSE: RTEC on the New York Stock Exchange, it is a provider of process and process control equipment and software for microelectronic manufacturing industries. The company's product offering includes automated defect inspection and metrology systems, probe card test and analysis systems, and lithography step-and-repeat systems. In addition, Rudolph provides a broad range of software products designed to improve yield, control processes and reduce manufacturing costs.

References

  1. "Startup enables IC variability characterization" by Richard Goering 2006
  2. "Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry" (abstract)
  3. Design for Manufacturability And Statistical Design: A Constructive Approach, by Michael Orshansky, Sani Nassif, Duane Boning 2007. ISBN   0-387-30928-4 ISBN   978-0-387-30928-6 p. 84

Bibliography