Chip-scale package

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A chip scale package or chip-scale package (CSP) is a type of integrated circuit package. [1]

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon 639-1 ısoo

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny transistors into a small chip results in circuits that are orders of magnitude smaller, cheaper, and faster than those constructed of discrete electronic components. The IC's mass production capability, reliability and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Contents

Originally, CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.

IPC (electronics) organization

IPC, the Association Connecting Electronics Industries, is a trade association whose aim is to standardize the assembly and production requirements of electronic equipment and assemblies. It was founded in 1957 as the Institute for Printed Circuits. Its name was later changed to the Institute for Interconnecting and Packaging Electronic Circuits to highlight the expansion from bare boards to packaging and electronic assemblies. In 1999, the organization formally changed its name to IPC with the accompanying tagline, Association Connecting Electronics Industries.

Die (integrated circuit) an unpackaged integrated circuit

A die, in the context of integrated circuits, is a small block of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor through processes such as photolithography. The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a die.

The concept was first proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable in 1993. The first concept demonstration however came from Mitsubishi Electric. [2]

Fujitsu Japanese multinational information technology equipment and services company

Fujitsu Ltd. is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. In 2015, it was the world's fourth-largest IT services provider measured by IT services revenue. Fortune named Fujitsu as one of the world's most admired companies and a Global 500 company.

Hitachi Cable, Ltd. was established in 1956 as a manufacturer of electric wire and cable for power distribution. The company, based in Tokyo, Japan, was formed from Hitachi Densen Works, the Hitachi Works spin-off previously known as Densen Works.

Mitsubishi Electric Japanese electronics and electrical equipments manufacturing company

Mitsubishi Electric Corporation is a Japanese multinational electronics and electrical equipment manufacturing company headquartered in Tokyo, Japan. It is one of the core companies of Mitsubishi.

The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer-level package (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as Advanced Semiconductor Engineering (ASE). [3] [4]

Interposer

An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Dept., Utica, N.Y. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry.

Ball grid array

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

Types

Example WL-CSP devices sitting on the face of a U.S. penny. A SOT-23 device is shown for comparison. UNIO WLCSP and SOT23 Device on Penny.jpg
Example WL-CSP devices sitting on the face of a U.S. penny. A SOT-23 device is shown for comparison.

Chip scale packages can be classified into the following groups:

  1. Customized leadframe-based CSP (LFCSP)
  2. Flexible substrate-based CSP
  3. Flip-chip CSP (FCCSP)
  4. Rigid substrate-based CSP
  5. Wafer-level redistribution CSP (WL-CSP)

Related Research Articles

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Pin grid array type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package

A pin grid array, often abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package.

Integrated circuit packaging Final stage of semiconductor device fabrication

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

IBM Solid Logic Technology

Solid Logic Technology (SLT) was IBM's method for packaging electronic circuitry introduced in 1964 with the IBM System/360 series and related machines. IBM chose to design custom hybrid circuits using discrete, flip chip-mounted, glass-encapsulated transistors and diodes, with silk screened resistors on a ceramic substrate, forming an SLT module. The circuits were either encapsulated in plastic or covered with a metal lid. Several of these SLT modules were then mounted on a small multi-layer printed circuit board to make an SLT card. Each SLT card had a socket on one edge that plugged into pins on the computer's backplane.

A system in package (SiP) or system-in-a-package is a number of integrated circuits enclosed in a single chip carrier package. The SiP performs all or most of the functions of an electronic system, and is typically used inside a mobile phone, digital music player, etc. Dies containing integrated circuits may be stacked vertically on a substrate. They are internally connected by fine wires that are bonded to the package. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together. Systems-in-package are like systems-on-chip (SoC) but less tightly integrated and not on a single semiconductor die.

Quad Flat No-leads package

Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).

Package on package

Package on package (PoP) is an integrated circuit packaging method to combine vertically discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras.

Through-silicon via

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

In microelectronics, a three-dimensional integrated circuit is an integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. 3D IC is just one of a host of 3D integration schemes that exploit the z-direction to achieve electrical performance benefits.

Integrated passive devices

Integrated Passive Devices (IPD's) "or Integrated Passive Components (IPC's)" are attracting an increasing interest due to constant needs of handheld wireless devices to further decrease in size and cost and increase in functionality.

Wafer-level packaging

Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment.

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting the package to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

Embedded Wafer Level Ball Grid Array

Embedded Wafer Level Ball Grid Array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.

Advanced Semiconductor Engineering, Inc., also known as ASE Group, is a provider of independent semiconductor assembling and test manufacturing services, with its headquarters in Kaohsiung, Taiwan.

Chip on board Circuit board manufacturing technique

Chip on board is the method of manufacturing where integrated circuits are wired and bonded directly to a printed circuit board. By eliminating the packaging of individual semiconductor devices, the completed product can be more compact, lighter, and less costly. In some cases chip on board construction improves the operation of radio frequency systems by reducing the inductance and capacitance of integrated circuit leads. Chip on board effectively merges two levels of electronic packaging, level 1 (components) and level 2, and may be referred to as a "level 1.5"

References

  1. "Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications". Application Note 4002. Maxim Integrated Products. April 18, 2007. Retrieved January 17, 2018.
  2. Puttlitz, Karl J.; Totta, Paul A. (December 6, 2012). Area Array Interconnection Handbook. Springer Science+Business Media. p. 702. ISBN   978-1-4615-1389-6.
  3. Prior, Brandon (January 22, 2001). "Wafer Scale Emerging". EDN . Retrieved March 31, 2016.
  4. "ASE Ramps Wafer Level CSP Production". EDN. October 12, 2001. Retrieved March 31, 2016.
JEDEC standards organization

The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body.