Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.
Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.
Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.
|SIP||Single in-line package|
|DIP||Dual in-line package||0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or 0.6 in (15.24 mm) apart.|
|CERDIP||Glass-sealed ceramic DIP|
|QIP||Quadruple in-line package||Like DIP but with staggered (zig-zag) pins.|
|SKDIP||Skinny DIP||Standard DIP with 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) apart.|
|SDIP||Shrink DIP||Non-standard DIP with smaller 0.07 in (1.78 mm) pin spacing.|
|ZIP||Zig-zag in-line package|
|CCGA||Ceramic column-grid array (CGA)|
|LLP||Lead-less lead-frame package||A package with metric pin distribution (0.5–0.8 mm pitch)|
|LGA||Land grid array|
|LTCC||Low-temperature co-fired ceramic|
|MICRO SMDXT||Micro surface-mount device extended technology||Example|
Chip on board is a packaging technique that directly connects a die to a PCB, without an interposer or lead frame.
A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.
|BCC||Bump chip carrier||-|
|CLCC||Ceramic lead-less chip carrier||-|
|LCC||Lead-less chip carrier||Contacts are recessed vertically.|
|LCC||Leaded chip carrier||-|
|LCCC||Leaded ceramic-chip carrier||-|
|DLCC||Dual lead-less chip carrier (ceramic)||-|
|PLCC||Plastic leaded chip carrier||-|
|OPGA||Organic pin-grid array||-|
|FCPGA||Flip-chip pin-grid array||-|
|PAC||Pin array cartridge||-|
|PGA||Pin-grid array||Also known as PPGA|
|CPGA||Ceramic pin-grid array||-|
|-||Flat-pack||Earliest version metal/ceramic packaging with flat leads|
|CQFP||Ceramic quad flat-pack||Similar to PQFP|
|BQFP||Bumpered quad flat-pack||-|
|DFN||Dual flat-pack||No lead|
|ETQFP||Exposed thin quad flat-package||-|
|PQFN||Power quad flat-pack||No-leads, with exposed die-pad[s] for heatsinking|
|PQFP||Plastic quad flat-package||-|
|LQFP||Low-profile quad flat-package||-|
|QFN||Quad flat no-leads package||Also called as micro lead frame (MLF).|
|QFP||Quad flat package||-|
|MQFP||Metric quad flat-pack||QFP with metric pin distribution|
|HVQFN||Heat-sink very-thin quad flat-pack, no-leads||-|
|SIDEBRAZE||[ clarification needed ]||[ clarification needed ]|
|TQFP||Thin quad flat-pack||-|
|VQFP||Very-thin quad flat-pack||-|
|TQFN||Thin quad flat, no-lead||-|
|VQFN||Very-thin quad flat, no-lead||-|
|WQFN||Very-very-thin quad flat, no-lead||-|
|UQFN||Ultra-thin quad flat-pack, no-lead||-|
|ODFN||Optical dual flat, no-lead||IC packaged in transparent packaging used in optical sensor|
|CSOP||Ceramic small-outline package|
|DSOP||Dual small-outline package|
|HSOP||Thermally-enhanced small-outline package|
|mini-SOIC||Mini small-outline integrated circuit|
|MSOP||Mini small-outline package|
|PSOP||Plastic small-outline package|
|PSON||Plastic small-outline no-lead package|
|QSOP||Quarter-size small-outline package||The pin spacing are width of 0.635 mm.|
|SOIC||Small-outline integrated circuit||Also known as SOIC NARROW and SOIC WIDE|
|SOJ||Small-outline J-leaded package|
|SON||Small-outline no-lead package|
|SSOP||Shrink small-outline package|
|TSOP||Thin small-outline package||Example|
|TSSOP||Thin shrink small-outline package|
|TVSOP||Thin very-small-outline package|
|µMAX||Similar to a SOIC. (A Maxim trademark example)|
|WSON||Very-very-thin small-outline no-lead package|
|USON||Very-very-thin small-outline no-lead package||Slightly smaller than WSON|
|BL||Beam lead technology||Bare silicon chip, an early chip-scale package|
|CSP||Chip-scale package||Package size is no more than 1.2× the size of the silicon chip|
|TCSP||True chip-size package||Package is same size as silicon|
|TDSP||True die-size package||Same as TCSP|
|WCSP or WL-CSP or WLCSP||Wafer-level chip-scale package|
|MICRO SMD||-||Chip-size package (CSP) developed by National Semiconductor|
|COB||Chip-on-board||Bare silicon chip, that is usually an integrated circuit, is supplied without a package. It can often be identified by having a blob of black Epoxy instead of a square package. Also used for LEDs. In LEDs, the epoxy is poured into a mold which forms part of the package.|
|COF||Chip-on-flex||Variation of COB, where a chip is mounted directly to a flex circuit.|
|TAB||Tape-automated bonding||Variation of COF, where a flip chip is mounted directly to a flex circuit without the use of bonding wires.|
|COG||Chip-on-glass||Variation of COB, where a chip is mounted directly to a piece of glass - typically an LCD.|
Ball Grid Array BGA uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.
|FBGA||Fine-pitch ball-grid array||A square or rectangular array of solder balls on one surface|
|LBGA||Low-profile ball-grid array||Also known as laminate ball-grid array|
|TEPBGA||Thermally-enhanced plastic ball-grid array||-|
|CBGA||Ceramic ball-grid array||-|
|OBGA||Organic ball-grid array||-|
|TFBGA||Thin fine-pitch ball-grid array||-|
|PBGA||Plastic ball-grid array||-|
|MAP-BGA||Mold array process - ball-grid array||-|
|UCSP||Micro (μ) chip-scale package||Similar to a BGA (A Maxim trademark example)|
|μBGA||Micro ball-grid array||Ball spacing less than 1 mm|
|LFBGA||Low-profile fine-pitch ball-grid array||-|
|TBGA||Thin ball-grid array||-|
|SBGA||Super ball-grid array||Above 500 balls|
|UFBGA||Ultra-fine ball-grid array|
All measurements below are given in mm . To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).
|DIP||Y||Dual inline package||8-DIP||6.2–6.48||7.62||7.7||9.2–9.8||2.54 (0.1 in)||3.05–3.6||1.14–1.73|
|32-DIP||15.24||2.54 (0.1 in)|
|LFCSP||N||Lead-frame chip-scale package||0.5|
|MSOP||Y||Mini small-outline package||8-MSOP||3||4.9||1.1||0.10||3||0.65||0.95||0.18||0.17–0.27|
|Y||Small-outline integrated circuit||8-SOIC||3.9||5.8–6.2||1.72||0.10–0.25||4.8–5.0||1.27||1.05||0.19–0.25||0.39–0.46|
|SSOP||Y||Shrink small-outline package||0.65|
|TDFN||N||Thin dual flat no-lead||8-TDFN||3||3||0.7–0.8||3||0.65||N/A||0.19–0.3|
|TSOP||Y||Thin small-outline package||0.5|
|TSSOP||Y||Thin shrink small-outline package||8-TSSOP||4.4||6.4||1.2||0.15||3||0.65||0.09–0.2||0.19–0.3|
|µSOP||Y||Micro small-outline package||µSOP-8||4.9||1.1||3||0.65|
|PLCC||N||Plastic leaded chip-carrier||1.27|
|CLCC||N||Ceramic leadless chip-carrier||48-CLCC||14.22||14.22||2.21||14.22||1.016||N/A||0.508|
|LQFP||Y||Low-profile Quad Flat Package||0.50|
|TQFP||Y||Thin quad flat-package||TQFP-44||10.00||12.00||0.35–0.50||0.80||1.00||0.09–0.20||0.30–0.45|
|TQFN||N||Thin quad flat no-lead|
|52-ULGA||12 mm||17 mm||0.65 mm|
|52-ULGA||14 mm||18 mm||0.10 mm|
A variety of techniques for interconnecting several chips within a single package have been proposed and researched:
In microelectronics, a dual in-line package, or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits. Increasingly complex circuits required more signal and power supply leads ; eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density chip carriers. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.
A printed circuit board (PCB) mechanically supports and electrically connects electrical or electronic components using conductive tracks, pads and other features etched from one or more sheet layers of copper laminated onto and/or between sheet layers of a non-conductive substrate. Components are generally soldered onto the PCB to both electrically connect and mechanically fasten them to it.
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.
Surface-mount technology (SMT) is a method in which the components are mounted or placed directly onto the surface of a printed circuit board (PCB). An electronic device so made is called a surface-mount device (SMD). In industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board, with the through-hole technology used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Dept., Utica, N.Y. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry.
In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.
The land grid array (LGA) is a type of surface-mount packaging for integrated circuits (ICs) that is notable for having the pins on the socket rather than the integrated circuit. A LGA can be electrically connected to a printed circuit board (PCB) either by the use of a socket or by soldering directly to the board.
A QFP or Quad Flat Package is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP).
In electronics, desoldering is the removal of solder and components from a circuit board for troubleshooting, repair, replacement, and salvage.
In electronics, a lead is an electrical connection consisting of a length of wire or a metal pad that is designed to connect two locations electrically. Leads are used for many purposes, including: transfer of power; testing of an electrical circuit to see if it is working, using a test light or a multimeter; transmitting information, as when the leads from an electrocardiograph are attached to a person's body to transmit information about their heart rhythm; and sometimes to act as a heatsink. The tiny leads coming off through-hole electronic components are also often called "pins"; in ball grid array packages, they are in form of small spheres, and are therefore called "balls".
A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. The convention for naming the package is SOIC or SO followed by the number of pins. For example, a 14-pin 4011 would be housed in an SOIC-14 or SO-14 package.
The TO-220 is a style of electronic package used for high-powered, through-hole components with 0.1 inches (2.54 mm) pin spacing. The "TO" designation stands for "transistor outline". TO-220 packages have three leads. Similar packages with two, four, five or seven leads are also manufactured. A notable characteristic is a metal tab with a hole, used in mounting the case to a heatsink, allowing the component to dissipate more heat than one constructed in a TO-92 case. Common TO-220-packaged components include discrete semiconductors such as transistors and silicon-controlled rectifiers, as well as integrated circuits.
A via or VIA is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. To ensure via robustness, IPC sponsored a round-robin exercise that developed a time to failure calculator.
Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).
Automated optical inspection (AOI) is an automated visual inspection of printed circuit board (PCB) manufacture where a camera autonomously scans the device under test for both catastrophic failure and quality defects. It is commonly used in the manufacturing process because it is a non-contact test method. It is implemented at many stages through the manufacturing process including bare board inspection, solder paste inspection (SPI), pre-reflow and post-reflow as well as other stages.
Bead probe technology (BPT) is technique used to provide electrical access to printed circuit board (PCB) circuitry for performing in-circuit testing (ICT). It makes use of small beads of solder placed onto the board's traces to allow measuring and controlling of the signals using a test probe. This permits test access to boards on which standard ICT test pads are not feasible due to space constraints.
A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting the package to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.
The D2PAK or DDPAK, standardized as TO-263, refers to a semiconductor package type intended for surface mounting on circuit boards. They are similar to the earlier TO-220-style packages intended for high power dissipation but lack the extended metal tab and mounting hole, while representing a larger version of the TO-252, also known as DPAK, SMT package. As with all SMT packages, the pins on a D2PAK are bent to lie against the PCB surface.
In electronics, a chip carrier is one of several kinds of surface-mount technology packages for integrated circuits. Connections are made on all four edges of a square package; Compared to the internal cavity for mounting the integrated circuit, the package overall size is large.
Chip on board (COB) is the method of manufacturing where integrated circuits are wired and bonded directly to a printed circuit board. By eliminating the packaging of individual semiconductor devices, the completed product can be more compact, lighter, and less costly. In some cases chip on board construction improves the operation of radio frequency systems by reducing the inductance and capacitance of integrated circuit leads. Chip on board effectively merges two levels of electronic packaging, level 1 (components) and level 2, and may be referred to as a "level 1.5"
|Wikimedia Commons has media related to Electronic component packages .|