List of integrated circuit packaging types

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A standard-sized 8-pin dual in-line package (DIP) containing a 555 IC. Signetics NE555N.JPG
A standard-sized 8-pin dual in-line package (DIP) containing a 555 IC.

Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon 639-1 ısoo

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny transistors into a small chip results in circuits that are orders of magnitude smaller, cheaper, and faster than those constructed of discrete electronic components. The IC's mass production capability, reliability and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting the package to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

JEDEC standards organization

The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body.


Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Dept., Utica, N.Y. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry.

Wire bonding

Wire bonding is the method of making interconnections (ATJ) between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC to other electronics or to connect from one printed circuit board (PCB) to another. Wire bonding is generally considered the most cost-effective and flexible interconnect technology and is used to assemble the vast majority of semiconductor packages. Wire bonding can be used at frequencies above 100 GHz.

Through-hole packages

Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.

Three 14-pin (DIP14) plastic dual in-line packages containing IC chips. Three IC circuit chips.JPG
Three 14-pin (DIP14) plastic dual in-line packages containing IC chips.
AcronymFull nameRemark
SIP Single in-line package
DIP Dual in-line package 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or 0.6 in (15.24 mm) apart.
CDIPCeramic DIP [1]
CERDIPGlass-sealed ceramic DIP [1]
QIP Quadruple in-line packageLike DIP but with staggered (zig-zag) pins. [1]
SKDIPSkinny DIP Standard DIP with 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) apart. [1]
SDIPShrink DIP Non-standard DIP with smaller 0.07 in (1.78 mm) pin spacing. [1]
ZIP Zig-zag in-line package
MDIPMolded DIP [2]
PDIPPlastic DIP [1]

Surface mount

AcronymFull nameRemark
CCGACeramic column-grid array (CGA) [3]
CGAColumn-grid array [3] Example
CERPACKCeramic package [4]
CQGP [5]
LLPLead-less lead-frame packageA package with metric pin distribution (0.5–0.8 mm pitch) [6]
LGA Land grid array [3]
LTCC Low-temperature co-fired ceramic [7]
MCM Multi-chip module [8]
MICRO SMDXTMicro surface-mount device extended technology [9] Example

Chip carrier

A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.

Chip carrier one of several kinds of surface mount technology packages for integrated circuits

In electronics, a chip carrier is one of several kinds of surface-mount technology packages for integrated circuits. Connections are made on all four edges of a square package; Compared to the internal cavity for mounting the integrated circuit, the package overall size is large.

AcronymFull nameRemark
BCCBump chip carrier [3] -
CLCCCeramic lead-less chip carrier [1] -
LCCLead-less chip carrier [3] Contacts are recessed vertically.
LCCLeaded chip carrier [3] -
LCCCLeaded ceramic-chip carrier [3] -
DLCCDual lead-less chip carrier (ceramic) [3] -
PLCCPlastic leaded chip carrier [1] [3] -

Pin grid arrays

AcronymFull nameRemark
OPGAOrganic pin-grid array-
FCPGAFlip-chip pin-grid array [3] -
PACPin array cartridge [10] -
PGAPin-grid arrayAlso known as PPGA [1]
CPGACeramic pin-grid array [3] -

Flat packages

AcronymFull nameRemark
- Flat-pack Earliest version metal/ceramic packaging with flat leads
CFPCeramic flat-pack [3] -
CQFPCeramic quad flat-pack [1] [3] Similar to PQFP
BQFPBumpered quad flat-pack [3] -
DFNDual flat-packNo lead [3]
ETQFPExposed thin quad flat-package [11] -
PQFNPower quad flat-packNo-leads, with exposed die-pad[s] for heatsinking [12]
PQFP Plastic quad flat-package [1] [3] -
LQFPLow-profile quad flat-package [3] -
QFN Quad flat no-leads package Also called as micro lead frame (MLF). [3] [13]
QFP Quad flat package [1] [3] -
MQFPMetric quad flat-packQFP with metric pin distribution [3]
HVQFNHeat-sink very-thin quad flat-pack, no-leads-
SIDEBRAZE [14] [15] [ clarification needed ][ clarification needed ]
TQFPThin quad flat-pack [1] [3] -
VQFPVery-thin quad flat-pack [3] -
TQFNThin quad flat, no-lead-
VQFNVery-thin quad flat, no-lead-
WQFNVery-very-thin quad flat, no-lead-
UQFNUltra-thin quad flat-pack, no-lead-
ODFNOptical dual flat, no-leadIC packaged in transparent packaging used in optical sensor

Small outline packages

AcronymFull nameRemark
SOP Small-outline package [1]
CSOPCeramic small-outline package
HSOPThermally-enhanced small-outline package
mini-SOIC Mini small-outline integrated circuit
MSOPMini small-outline package
PSOPPlastic small-outline package [3]
PSONPlastic small-outline no-lead package
QSOPQuarter-size small-outline packageThe pin spacing are width of 0.635 mm. [3]
SOIC Small-outline integrated circuitAlso known as SOIC NARROW and SOIC WIDE
SOJ Small-outline J-leaded package
SSOP Shrink small-outline package [3]
TSOP Thin small-outline package [3] Example
TSSOP Thin shrink small-outline package [3]
TVSOPThin very-small-outline package [3]
µMAXSimilar to a SOIC. (A Maxim trademark example)
WSONVery-very-thin small-outline no-lead package

Chip-scale packages

Example WL-CSP devices sitting on the face of a U.S. penny. A SOT-23 device is shown for comparison. UNIO WLCSP and SOT23 Device on Penny.jpg
Example WL-CSP devices sitting on the face of a U.S. penny. A SOT-23 device is shown for comparison.
AcronymFull nameRemark
BL Beam lead technology Bare silicon chip, an early chip-scale package
CSP Chip-scale packagePackage size is no more than 1.2× the size of the silicon chip [16] [17]
TCSPTrue chip-size packagePackage is same size as silicon [18]
TDSPTrue die-size packageSame as TCSP [18]
WCSP Wafer-level chip-scale package
MICRO SMD-Chip-size package (CSP) developed by National Semiconductor [19]
COBChip-on-boardBare silicon chip, that is usually an integrated circuit, is supplied without a package.
COFChip-on-flexVariation of COB, where a chip is mounted directly to a flex circuit.
COGChip-on-glassVariation of COB, where a chip is mounted directly to a piece of glass - typically an LCD.

Ball grid array

Ball Grid Array BGA uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB. [1] [3]

Ball grid array

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

AcronymFull nameRemark
FBGA Fine-pitch ball-grid arrayA square or rectangular array of solder balls on one surface [3]
LBGALow-profile ball-grid arrayAlso known as laminate ball-grid array [3]
TEPBGAThermally-enhanced plastic ball-grid array-
CBGACeramic ball-grid array [3] -
OBGAOrganic ball-grid array [3] -
TFBGAThin fine-pitch ball-grid array [3] -
PBGAPlastic ball-grid array [3] -
MAP-BGAMold array process - ball-grid array -
UCSPMicro (μ) chip-scale packageSimilar to a BGA (A Maxim trademark example) [17]
μBGAMicro ball-grid arrayBall spacing less than 1 mm
LFBGALow-profile fine-pitch ball-grid array [3] -
TBGAThin ball-grid array [3] -
SBGASuper ball-grid array [3] Above 500 balls
UFBGAUltra-fine ball-grid array [3]

Transistor, diode, small-pin-count IC packages

A drawing of a ZN414 IC in a TO-18 package TO-18, 3 leads, ZN414 (shaded).svg
A drawing of a ZN414 IC in a TO-18 package
Small-outline transistor

A small outline transistor (SOT) is a family of small footprint, discrete surface mount transistor commonly used in consumer electronics. The most common SOT are SOT23 variations, also manufacturers offer the nearly identical thin small outline transistor (TSOT) package, where lower height is important.


In electronics, TO-3 is a designation for a standardized metal semiconductor package used for power semiconductors, including transistors, silicon controlled rectifiers, and, integrated circuits. TO stands for "Transistor Outline" and relates to a series of technical drawings produced by JEDEC.

TO-5 designation for a standardized metal semiconductor package

In electronics, TO-5 is a designation for a standardized metal semiconductor package used for transistors and some integrated circuits. The TO element stands for "transistor outline" and refers to a series of technical drawings produced by JEDEC.

Dimension reference


A general surface mount chip, with major dimensions. SOIC Dimensions.gif
A general surface mount chip, with major dimensions.
Clearance between IC body and PCB
Total Height
Lead Thickness
Total carrier length
Lead width
Lead length


A general through-hole pin chip, with major dimensions. DIP Dimension Labels.svg
A general through-hole pin chip, with major dimensions.
Clearance between IC body and board
Total height
Lead thickness
Total carrier length
Lead width
Lead length
IC body width
Lead-to-lead width

Package dimensions

All measurements below are given in mm . To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).

Clearance between package body and PCB.
Height of package from pin tip to top of package.
Thickness of pin.
Length of package body only.
Pin width.
Pin length from package to pin tip.
Pin pitch (distance between conductors to the PCB).
Width of the package body only.
Length from pin tip to pin tip on the opposite side.

Dual row

Three IC circuit chips.JPG DIP YDual inline package8-DIP6.2–6.487.627.79.2–9.82.54 (0.1 in)3.05–3.61.14–1.73
32-DIP15.242.54 (0.1 in)
LFCSP NLead-frame chip-scale package0.5
MSOP-sized chip package.jpg MSOP YMini small-outline package8-MSOP34.91.10.1030.650.950.180.17–0.27
MFrey SOIC20.jpg SO
YSmall-outline integrated circuit8-SOIC3.95.8–6.21.720.10–0.254.8––0.250.39–0.46
SOT23-6.jpg SOT YSmall-outline transistorSOT-23-–0.38
SSOP YShrink small-outline package0.65
TDFN NThin dual flat no-lead8-TDFN330.7–0.830.65N/A0.19–0.3
TSOP YThin small-outline package0.5
TSSOP EXP PAD 16L.gif TSSOP YThin shrink small-outline package8-TSSOP4.–0.20.19–0.3
µSOP YMicro small-outline package [22] µSOP-
US8 [23] YUS8 package2.33.1.720.5

Quad rows

Qfj52.jpg PLCC NPlastic leaded chip-carrier1.27
CLCC NCeramic leadless chip-carrier48-CLCC14.2214.222.2114.221.016N/A0.508
Cyrix cx9210 gfdl.jpg LQFP YLow-profile Quad Flat Package0.50
PIC18F8720.jpg TQFP YThin quad flat-packageTQFP-4410.0012.000.35–0.500.801.000.09–0.200.30–0.45
TQFN NThin quad flat no-lead


52-ULGA12 mm17 mm0.65 mm
52-ULGA14 mm18 mm0.10 mm

Multi-chip packages

A variety of techniques for interconnecting several chips within a single package have been proposed and researched:

See also

Related Research Articles

Dual in-line package

In microelectronics, a dual in-line package, or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits. Increasingly complex circuits required more signal and power supply leads ; eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density packages. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.

Printed circuit board board to support and connect electronic components

A printed circuit board (PCB) mechanically supports and electrically connects electronic components or electrical components using conductive tracks, pads and other features etched from one or more sheet layers of copper laminated onto and/or between sheet layers of a non-conductive substrate. Components are generally soldered onto the PCB to both electrically connect and mechanically fasten them to it.

Surface-mount technology method for producing electronic circuits

Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBs). An electronic device so made is called a surface-mount device (SMD). In industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board, with the through-hole technology used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.

Integrated circuit packaging Final stage of semiconductor device fabrication

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

Quad Flat Package surface mount integrated circuit package

A QFP or Quad Flat Package is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP).


In electronics, desoldering is the removal of solder and components from a circuit board for troubleshooting, repair, replacement, and salvage.

Lead (electronics) connecting wire or pad within an electronic device; electrical connection consisting of a length of wire or metal pad (SMD) that comes from a device

In electronics, a lead is an electrical connection consisting of a length of wire or a metal pad (SMD) that is designed to connect two locations electrically. Leads are used for many purposes, including: transfer of power; testing of an electrical circuit to see if it is working, using a test light or a multimeter; transmiting information, as when the leads from an electrocardiograph, or ECG are attached to a person's body to transmit information about their heart rhythm; and sometimes to act as a heatsink. The tiny leads coming off through-hole components are also often called pins.

Small Outline Integrated Circuit

A Small Outline Integrated Circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. The convention for naming the package is SOIC or SO followed by the number of pins. For example, a 14-pin 4011 would be housed in an SOIC-14 or SO-14 package.


The TO-220 is a style of electronic package used for high-powered, through-hole components. The "TO" designation stands for "transistor outline". TO-220 packages have three leads. Similar packages with two, four, five or seven leads are also manufactured. A notable characteristic is a metal tab with a hole, used in mounting the case to a heatsink, allowing the component to dissipate more heat than one constructed in a TO-92 case. Common TO-220-packaged components include discrete semiconductors such as transistors and silicon-controlled rectifiers, as well as integrated circuits.

Quad Flat No-leads package

Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).

Bead probe technology

Bead probe technology (BPT) is technique used to provide electrical access to printed circuit board (PCB) circuitry for performing in-circuit testing (ICT). It makes use of small beads of solder placed onto the board's traces to allow measuring and controlling of the signals using a test probe. This permits test access to boards on which standard ICT test pads are not feasible due to space constraints.

Footprint (electronics)

A footprint or land pattern is the arrangement of pads or through-holes used to physically attach and electrically connect a component to a printed circuit board. The land pattern on a circuit board matches the arrangement of leads on a component.


The D2PAK or DDPAK, standardized as TO-263, refers to a semiconductor package type intended for surface mounting on circuit boards. They are similar to the earlier TO-220-style packages intended for high power dissipation but lack the extended metal tab and mounting hole, while representing a larger version of the TO-252, also known as DPAK, SMT package. As with all SMT packages, the pins on a D2PAK are bent to lie against the PCB surface.

Chip on board Circuit board manufacturing technique

Chip on board is the method of manufacturing where integrated circuits are wired and bonded directly to a printed circuit board. By eliminating the packaging of individual semiconductor devices, the completed product can be more compact, lighter, and less costly. In some cases chip on board construction improves the operation of radio frequency systems by reducing the inductance and capacitance of integrated circuit leads. Chip on board effectively merges two levels of electronic packaging, level 1 (components) and level 2, and may be referred to as a "level 1.5"


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