Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of package types exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.
Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.
Through-hole technology uses holes drilled through the printed circuit board (PCB) for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.
Acronym | Full name | Remark |
---|---|---|
SIP | Single in-line package | |
DIP | Dual in-line package | 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or 0.6 in (15.24 mm) apart. Other row spacings are used much less frequently, like 0.4 in (10.2 mm) and 0.9 in (22.9 mm). |
CDIP | Ceramic DIP [1] | |
CERDIP | Glass-sealed ceramic DIP [1] | |
QIP | Quad in-line package | Like DIP but with staggered (zig-zag) pins. [1] |
SKDIP | Skinny DIP | Standard DIP with 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) apart. [1] |
SDIP | Shrink DIP | Non-standard DIP with smaller 0.07 in (1.78 mm) pin spacing. [1] |
ZIP | Zig-zag in-line package | |
MDIP | Molded DIP [2] | |
PDIP | Plastic DIP [1] |
Acronym | Full name | Remark |
---|---|---|
CCGA | Ceramic column-grid array (CGA) [3] | |
CGA | Column-grid array [3] | |
CERPACK | Ceramic package [4] | |
CQGP [5] | Ceramic Quad Grid Array Package | |
LLP | Lead-less lead-frame package | A package with metric pin distribution (0.5–0.8 mm pitch) [6] |
LGA | Land grid array [3] | |
LTCC | Low-temperature co-fired ceramic [7] | |
MCM | Multi-chip module [8] | |
MICRO SMDXT | Micro surface-mount device extended technology [9] |
Chip on board is a packaging technique that directly connects a die to a PCB, without an interposer or lead frame.
A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.
Acronym | Full name | Remark |
---|---|---|
BCC | Bump chip carrier [3] | |
CLCC | Ceramic lead-less chip carrier [1] | |
LCC | Lead-less chip carrier [3] | Contacts are recessed vertically. |
LCC | Leaded chip carrier [3] | |
LCCC | Leaded ceramic-chip carrier [3] | |
DLCC | Dual lead-less chip carrier (ceramic) [3] | |
PLCC | Plastic leaded chip carrier [1] [3] |
Acronym | Full name | Remark |
---|---|---|
OPGA | Organic pin-grid array | |
FCPGA | Flip-chip pin-grid array [3] | |
PGA | Pin-grid array | Also known as PPGA [1] |
CPGA | Ceramic pin-grid array [3] |
Acronym | Full name | Remark |
---|---|---|
- | Flat-pack | Earliest version metal/ceramic packaging with flat leads |
CFP | Ceramic flat-pack [3] | |
CQFP | Ceramic quad flat-pack [1] [3] | Similar to PQFP |
BQFP | Bumpered quad flat-pack [3] | |
DFN | Dual flat-pack | No lead [3] |
ETQFP | Exposed thin quad flat-package [10] | |
PQFN | Power quad flat-pack | No-leads, with exposed die-pad[s] for heatsinking [11] |
PQFP | Plastic quad flat-package [1] [3] | |
LQFP | Low-profile quad flat-package [3] | |
QFN | Quad flat no-leads package | Also called as micro lead frame (MLF). [3] [12] |
QFP | Quad flat package [1] [3] | |
MQFP | Metric quad flat-pack | QFP with metric pin distribution [3] |
HVQFN | Heat-sink very-thin quad flat-pack, no-leads | |
SIDEBRAZE [13] [14] | [ clarification needed ] | [ clarification needed ] |
TQFP | Thin quad flat-pack [1] [3] | |
VQFP | Very-thin quad flat-pack [3] | |
TQFN | Thin quad flat, no-lead | |
VQFN | Very-thin quad flat, no-lead | |
WQFN | Very-very-thin quad flat, no-lead | |
UQFN | Ultra-thin quad flat-pack, no-lead | |
ODFN | Optical dual flat, no-lead | IC packaged in transparent packaging used in optical sensor |
A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs.
Acronym | Full name | Remark |
---|---|---|
SOP | Small-outline package [1] | |
CSOP | Ceramic small-outline package | |
DSOP | Dual small-outline package | |
HSOP | Thermally-enhanced small-outline package | |
HSSOP | Thermally-enhanced shrink small-outline package [15] | |
HTSSOP | Thermally-enhanced thin shrink small-outline package [15] | |
mini-SOIC | Mini small-outline integrated circuit | |
MSOP | Mini small-outline package | Maxim uses the trademarked name μMAX for MSOP packages |
PSOP | Plastic small-outline package [3] | |
PSON | Plastic small-outline no-lead package | |
QSOP | Quarter-size small-outline package | The terminal pitch is 0.635 mm. [3] |
SOIC | Small-outline integrated circuit | Also known as SOIC NARROW and SOIC WIDE |
SOJ | Small-outline J-leaded package | |
SON | Small-outline no-lead package | |
SSOP | Shrink small-outline package [3] | |
TSOP | Thin small-outline package [3] | |
TSSOP | Thin shrink small-outline package [3] | |
TVSOP | Thin very-small-outline package [3] | |
VSOP | Very-small-outline package [15] | |
VSSOP | Very-thin shrink small-outline package [15] | Also referred as MSOP = micro small-outline package |
WSON | Very-very-thin small-outline no-lead package | |
USON | Very-very-thin small-outline no-lead package | Slightly smaller than WSON |
According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm. Chip-scale package
Acronym | Full name | Remark |
---|---|---|
BL | Beam lead technology | Bare silicon chip, an early chip-scale package |
CSP | Chip-scale package | Package size is no more than 1.2× the size of the silicon chip [16] [17] |
TCSP | True chip-size package | Package is same size as silicon [18] |
TDSP | True die-size package | Same as TCSP [18] |
WCSP or WL-CSP or WLCSP | Wafer-level chip-scale package | A WL-CSP or WLCSP package is just a bare die with a redistribution layer (or I/O pitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like a BGA package. [19] |
PMCP | Power mount CSP (chip-scale package) | Variation of WLCSP, for power devices like MOSFETs. Made by Panasonic. [20] |
Fan-out WLCSP | Fan-out wafer-level packaging | Variation of WLCSP. Like a BGA package but with the interposer built directly atop the die and encapsulated alongside it. |
eWLB | Embedded wafer level ball grid array | Variation of WLCSP. |
MICRO SMD | - | Chip-size package (CSP) developed by National Semiconductor [21] |
COB | Chip on board | Bare die supplied without a package. It is mounted directly to the PCB using bonding wires and covered with a blob of black Epoxy. [22] Also used for LEDs. In LEDs, transparent epoxy or a silicon caulk-like material that may contain a phosphor is poured into a mold containing the LED(s) and cured. The mold forms part of the package. |
COF | Chip-on-flex | Variation of COB, where a chip is mounted directly to a flex circuit. Unlike COB, it may not use wires nor be covered with epoxy, using underfill instead. |
TAB | Tape-automated bonding | Variation of COF, where a flip chip is mounted directly to a flex circuit without the use of bonding wires. Used by LCD driver ICs. |
COG | Chip-on-glass | Variation of TAB, where a chip is mounted directly to a piece of glass - typically an LCD. Used by LCD and OLED driver ICs. |
Ball grid array (BGA) uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB. [1] [3]
Acronym | Full name | Remark |
---|---|---|
FBGA | Fine-pitch ball-grid array | A square or rectangular array of solder balls on one surface [3] |
LBGA | Low-profile ball-grid array | Also known as laminate ball-grid array [3] |
TEPBGA | Thermally-enhanced plastic ball-grid array | |
CBGA | Ceramic ball-grid array [3] | |
OBGA | Organic ball-grid array [3] | |
TFBGA | Thin fine-pitch ball-grid array [3] | |
PBGA | Plastic ball-grid array [3] | |
MAP-BGA | Mold array process - ball-grid array | |
UCSP | Micro (μ) chip-scale package | Similar to a BGA (A Maxim trademark example) [17] |
μBGA | Micro ball-grid array | Ball spacing less than 1 mm |
LFBGA | Low-profile fine-pitch ball-grid array [3] | |
TBGA | Thin ball-grid array [3] | |
SBGA | Super ball-grid array [3] | Above 500 balls |
UFBGA | Ultra-fine ball-grid array [3] |
All measurements below are given in mm . To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).
Image | Family | Pin | Name | Package | L | WB | WL | H | C | P | LL | T | LW |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIP | Y | Dual inline package | 8-DIP | 9.2–9.8 | 6.2–6.48 | 7.62 | 7.7 | 2.54 (0.1 in) | 3.05–3.6 | 1.14–1.73 | |||
32-DIP | 15.24 | 2.54 (0.1 in) | |||||||||||
LFCSP | N | Lead-frame chip-scale package | 0.5 | ||||||||||
MSOP | Y | Mini small-outline package | 8-MSOP | 3 | 3 | 4.9 | 1.1 | 0.10 | 0.65 | 0.95 | 0.18 | 0.17–0.27 | |
10-MSOP | 3 | 3 | 4.9 | 1.1 | 0.10 | 0.5 | 0.95 | 0.18 | 0.17–0.27 | ||||
16-MSOP | 4.04 | 3 | 4.9 | 1.1 | 0.10 | 0.5 | 0.95 | 0.18 | 0.17–0.27 | ||||
SO SOIC SOP | Y | Small-outline integrated circuit | 8-SOIC | 4.8–5.0 | 3.9 | 5.8–6.2 | 1.72 | 0.10–0.25 | 1.27 | 1.05 | 0.19–0.25 | 0.39–0.46 | |
14-SOIC | 8.55–8.75 | 3.9 | 5.8–6.2 | 1.72 | 0.10–0.25 | 1.27 | 1.05 | 0.19–0.25 | 0.39–0.46 | ||||
16-SOIC | 9.9–10 | 3.9 | 5.8–6.2 | 1.72 | 0.10–0.25 | 1.27 | 1.05 | 0.19–0.25 | 0.39–0.46 | ||||
16-SOIC | 10.1–10.5 | 7.5 | 10.00–10.65 | 2.65 | 0.10–0.30 | 1.27 | 1.4 | 0.23–0.32 | 0.38–0.40 | ||||
SOT | Y | Small-outline transistor | SOT-23-6 | 2.9 | 1.6 | 2.8 | 1.45 | 0.95 | 0.6 | 0.22–0.38 | |||
SSOP | Y | Shrink small-outline package | 0.65 | ||||||||||
TDFN | N | Thin dual flat no-lead | 8-TDFN | 3 | 3 | 3 | 0.7–0.8 | 0.65 | — | 0.19–0.3 | |||
TSOP | Y | Thin small-outline package | 0.5 | ||||||||||
TSSOP | Y | Thin shrink small-outline package | 8-TSSOP [25] | 2.9-3.1 | 4.3-4.5 | 6.4 | 1.2 | 0.15 | 0.65 | 0.09–0.2 | 0.19–0.3 | ||
Y | 14-TSSOP [26] | 4.9-5.1 | 4.3-4.5 | 6.4 | 1.1 | 0.05-0.15 | 0.65 | 0.09-0.2 | 0.19-0.30 | ||||
20-TSSOP [27] | 6.4-6.6 | 4.3-4.5 | 6.4 | 1.1 | .05-0.15 | 0.65 | 0.09-0.2 | 0.19-0.30 | |||||
μSOP | Y | Micro small-outline package [28] | μSOP-8 | 3 | 4.9 | 1.1 | 0.65 | ||||||
US8 [29] | Y | US8 package | 2 | 2.3 | 3.1 | .7 | 0.5 |
Image | Family | Pin | Name | Package | WB | WL | H | C | L | P | LL | T | LW |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLCC | N | Plastic leaded chip-carrier | 1.27 | ||||||||||
CLCC | N | Ceramic leadless chip-carrier | 48-CLCC | 14.22 | 14.22 | 2.21 | 14.22 | 1.016 | — | 0.508 | |||
LQFP | Y | Low-profile quad flat package | 0.50 | ||||||||||
TQFP | Y | Thin quad flat-package | TQFP-44 | 10.00 | 12.00 | 0.35–0.50 | 0.80 | 1.00 | 0.09–0.20 | 0.30–0.45 | |||
TQFN | N | Thin quad flat no-lead |
Package | x | y | z |
---|---|---|---|
52-ULGA | 12 mm | 17 mm | 0.65 mm |
52-ULGA | 14 mm | 18 mm | 0.10 mm |
52-VELGA | ? | ? | ? |
A variety of techniques for interconnecting several chips within a single package have been proposed and researched:
Surface-mount components are usually smaller than their counterparts with leads, and are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes (the leading standardisation body is JEDEC).
The codes given in the chart below usually tell the length and width of the components in tenths of millimeters or hundredths of inches. For example, a metric 2520 component is 2.5 mm by 2.0 mm which corresponds roughly to 0.10 inches by 0.08 inches (hence, imperial size is 1008). Exceptions occur for imperial in the two smallest rectangular passive sizes. The metric codes still represent the dimensions in mm, even though the imperial size codes are no longer aligned. Problematically, some manufacturers are developing metric 0201 components with dimensions of 0.25 mm × 0.125 mm (0.0098 in × 0.0049 in), [31] but the imperial 01005 name is already being used for the 0.4 mm × 0.2 mm (0.0157 in × 0.0079 in) package. These increasingly small sizes, especially 0201 and 01005, can sometimes be a challenge from a manufacturability or reliability perspective. [32]
Mostly resistors and capacitors.
Package | Approximate dimensions, length × width | Typical resistor power rating (W) | ||
---|---|---|---|---|
Metric | Imperial | |||
0201 | 008004 | 0.25 mm × 0.125 mm | 0.010 in × 0.005 in | |
03015 | 009005 | 0.3 mm × 0.15 mm | 0.012 in × 0.006 in | 0.02 [33] |
0402 | 01005 | 0.4 mm × 0.2 mm | 0.016 in × 0.008 in | 0.031 [34] |
0603 | 0201 | 0.6 mm × 0.3 mm | 0.02 in × 0.01 in | 0.05 [34] |
1005 | 0402 | 1.0 mm × 0.5 mm | 0.04 in × 0.02 in | 0.062 [35] –0.1 [34] |
1608 | 0603 | 1.6 mm × 0.8 mm | 0.06 in × 0.03 in | 0.1 [34] |
2012 | 0805 | 2.0 mm × 1.25 mm | 0.08 in × 0.05 in | 0.125 [34] |
2520 | 1008 | 2.5 mm × 2.0 mm | 0.10 in × 0.08 in | |
3216 | 1206 | 3.2 mm × 1.6 mm | 0.125 in × 0.06 in | 0.25 [34] |
3225 | 1210 | 3.2 mm × 2.5 mm | 0.125 in × 0.10 in | 0.5 [34] |
4516 | 1806 | 4.5 mm × 1.6 mm | 0.18 in × 0.06 in [36] | |
4532 | 1812 | 4.5 mm × 3.2 mm | 0.18 in × 0.125 in | 0.75 [34] |
4564 | 1825 | 4.5 mm × 6.4 mm | 0.18 in × 0.25 in | 0.75 [34] |
5025 | 2010 | 5.0 mm × 2.5 mm | 0.20 in × 0.10 in | 0.75 [34] |
6332 | 2512 | 6.3 mm × 3.2 mm | 0.25 in × 0.125 in | 1 [34] |
6863 | 2725 | 6.9 mm × 6.3 mm | 0.27 in × 0.25 in | 3 |
7451 | 2920 | 7.4 mm × 5.1 mm | 0.29 in × 0.20 in [37] |
Package | Dimensions (Length, typ. × width, typ. × height, max.) |
---|---|
EIA 2012-12 (KEMET R, AVX R) | 2.0 mm × 1.3 mm × 1.2 mm |
EIA 3216-10 (KEMET I, AVX K) | 3.2 mm × 1.6 mm × 1.0 mm |
EIA 3216-12 (KEMET S, AVX S) | 3.2 mm × 1.6 mm × 1.2 mm |
EIA 3216-18 (KEMET A, AVX A) | 3.2 mm × 1.6 mm × 1.8 mm |
EIA 3528-12 (KEMET T, AVX T) | 3.5 mm × 2.8 mm × 1.2 mm |
EIA 3528-21 (KEMET B, AVX B) | 3.5 mm × 2.8 mm × 2.1 mm |
EIA 6032-15 (KEMET U, AVX W) | 6.0 mm × 3.2 mm × 1.5 mm |
EIA 6032-28 (KEMET C, AVX C) | 6.0 mm × 3.2 mm × 2.8 mm |
EIA 7260-38 (KEMET E, AVX V) | 7.2 mm × 6.0 mm × 3.8 mm |
EIA 7343-20 (KEMET V, AVX Y) | 7.3 mm × 4.3 mm × 2.0 mm |
EIA 7343-31 (KEMET D, AVX D) | 7.3 mm × 4.3 mm × 3.1 mm |
EIA 7343-43 (KEMET X, AVX E) | 7.3 mm × 4.3 mm × 4.3 mm |
Package | Dimensions (Length, typ. × width, typ. × height, max.) |
---|---|
Cornell-Dubilier A | 3.3 mm × 3.3 mm × 5.5 mm |
Chemi-Con D | 4.3 mm × 4.3 mm × 5.7 mm |
Panasonic B | 4.3 mm × 4.3 mm × 6.1 mm |
Chemi-Con E | 5.3 mm × 5.3 mm × 5.7 mm |
Panasonic C | 5.3 mm × 5.3 mm × 6.1 mm |
Chemi-Con F | 6.6 mm × 6.6 mm × 5.7 mm |
Panasonic D | 6.6 mm × 6.6 mm × 6.1 mm |
Panasonic E/F, Chemi-Con H | 8.3 mm × 8.3 mm × 6.5 mm |
Panasonic G, Chemi-Con J | 10.3 mm × 10.3 mm × 10.5 mm |
Chemi-Con K | 13 mm × 13 mm × 14 mm |
Panasonic H | 13.5 mm × 13.5 mm × 14 mm |
Panasonic J, Chemi-Con L | 17 mm × 17 mm × 17 mm |
Panasonic K, Chemi-Con M | 19 mm × 19 mm × 17 mm |
Package | Dimensions (Length, typ. × width, typ. × height, max.) |
---|---|
SOD-80C | 3.5 mm × ⌀ 1.5 mm [43] |
SOD-123 | 2.65 mm × 1.6 mm × 1.35 mm [44] |
SOD-128 | 3.8 mm × 2.5 mm × 1.1 mm [45] |
SOD-323 (SC-76) | 1.7 mm × 1.25 mm × 1.1 mm [46] |
SOD-523 (SC-79) | 1.2 mm × 0.8 mm × 0.65 mm [47] |
SOD-723 | 1.0 mm × 0.6 mm × 0.65 mm [48] |
SOD-923 | 0.8 mm × 0.6 mm × 0.4 mm [49] |
Mostly resistors and diodes; barrel shaped components, dimensions do not match those of rectangular references for identical codes. [50]
Package | Dimensions | Typical resistor rating | |
---|---|---|---|
Power (W) | Voltage (V) | ||
MicroMELF (MMU), 0102 | 2.2 mm × ⌀ 1.1 mm | 0.2–0.3 | 150 |
MiniMELF (MMA), 0204 | 3.6 mm × ⌀ 1.4 mm | 0.25–0.4 | 200 |
MELF (MMB), 0207 | 5.8 mm × ⌀ 2.2 mm | 0.4–1.0 | 300 |
Commonly used for rectifier, Schottky, and other diodes.
Package | Dimensions (incl. leads) (Length, typ. × width, typ. × height, max.) |
---|---|
DO-214AA (SMB) | 5.4 mm × 3.6 mm × 2.65 mm [51] |
DO-214AB (SMC) | 7.95 mm × 5.9 mm × 2.25 mm [51] |
DO-214AC (SMA) | 5.2 mm × 2.6 mm × 2.15 mm [51] |
Package | Aliases | Dimensions (excl. leads) (Length, typ. × width, typ. × height, max.) | Number of terminals | Remark |
---|---|---|---|---|
SOT-23-3 | TO-236-3, SC-59 | 2.92 mm × 1.3 mm × 1.12 mm [52] | 3 | |
SOT-89 | TO-243, [53] SC-62 [54] | 4.5 mm × 2.5 mm × 1.5 mm [55] | 4 | Center pin is connected to a large heat-transfer pad |
SOT-143 | TO-253 | 2.9 mm × 1.3 mm × 1.22 mm [56] | 4 | Tapered body, one larger pad denotes terminal 1 |
SOT-223 | TO-261 | 6.5 mm × 3.5 mm × 1.8 mm [57] | 4 | One terminal is a large heat-transfer pad |
SOT-323 | SC-70 | 2 mm × 1.25 mm × 1.1 mm [58] | 3 | |
SOT-416 | SC-75 | 1.6 mm × 0.8 mm × 0.9 mm [59] | 3 | |
SOT-663 | 1.6 mm × 1.2 mm × 0.6 mm [60] | 3 | ||
SOT-723 | 1.2 mm × 0.8 mm × 0.55 [61] | 3 | Has flat leads | |
SOT-883 | SC-101 | 1 mm × 0.6 mm × 0.5 mm [62] | 3 | Is lead-less |
Package | Aliases | Dimensions (excl. leads) (Length, typ. × width, typ. × height, max.) | Number of terminals | Leaded or leadless |
---|---|---|---|---|
SOT-23-6 | SOT-26, SC-74 | 2.9 mm × 1.3 mm × 1.3 mm [68] | 6 | Leaded |
SOT-353 | SC-88A | 2 mm × 1.25 mm × 0.95 mm [69] | 5 | Leaded |
SOT-363 | SC-88, SC-70-6 | 2 mm × 1.25 mm × 0.95 mm [70] | 6 | Leaded |
SOT-563 | 1.6 mm × 1.2 mm × 0.6 mm [71] | 6 | Leaded | |
SOT-665 | 1.6 mm × 1.6 mm × 0.55 mm [72] | 5 | Leaded | |
SOT-666 | 1.6 mm × 1.2 mm × 0.6 mm [73] | 6 | Leaded | |
SOT-886 | 1.45 mm × 1 mm × 0.5 mm [74] | 6 | Leadless | |
SOT-891 | 1 mm × 1 mm × 0.5 mm [75] | 6 | Leadless | |
SOT-953 | 1 mm × 0.8 mm × 0.5 mm [76] | 5 | Leaded | |
SOT-963 | 1 mm × 1 mm × 0.5 mm [77] | 6 | Leaded | |
SOT-1115 | 1 mm × 0.9 mm × 0.35 mm [78] | 6 | Leadless | |
SOT-1202 | 1 mm × 1 mm × 0.35 mm [79] | 6 | Leadless |
Although surface-mount, these devices require specific process for assembly.
There are often subtle variations in package details from manufacturer to manufacturer, and even though standard designations are used, designers need to confirm dimensions when laying out printed circuit boards.
In microelectronics, a dual in-line package is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits. Increasingly complex circuits required more signal and power supply leads ; eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density chip carriers. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.
Surface-mount technology (SMT), originally called planar mounting, is a method in which the electrical components are mounted directly onto the surface of a printed circuit board (PCB). An electrical component mounted in this manner is referred to as a surface-mount device (SMD). In industry, this approach has largely replaced the through-hole technology construction method of fitting components, in large part because SMT allows for increased manufacturing automation which reduces cost and improves quality. It also allows for more components to fit on a given area of substrate. Both technologies can be used on the same board, with the through-hole technology often used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.
A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package.
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Department, Utica, New York. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and fine wires are welded onto the chip pads and lead frame contacts to interconnect the chip pads to external circuitry.
Integrated circuit packaging is the final stage of semiconductor device fabrication, in which the die is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.
In computer hardware, a CPU socket or CPU slot contains one or more mechanical components providing mechanical and electrical connections between a microprocessor and a printed circuit board (PCB). This allows for placing and replacing the central processing unit (CPU) without soldering.
A quad flat package (QFP) is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP).
Thin small outline package (TSOP) is a type of surface mount IC package. They are very low-profile and have tight lead spacing.
A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. The convention for naming the package is SOIC or SO followed by the number of pins. For example, a 14-pin 4011 would be housed in an SOIC-14 or SO-14 package.
The TO-220 is a style of electronic package used for high-powered, through-hole components with 0.1 inches (2.54 mm) pin spacing. The "TO" designation stands for "transistor outline". TO-220 packages have three leads. Similar packages with two, four, five or seven leads are also manufactured. A notable characteristic is a metal tab with a hole, used to mount the case to a heatsink, allowing the component to dissipate more heat than one constructed in a TO-92 case. Common TO-220-packaged components include discrete semiconductors such as transistors and silicon-controlled rectifiers, as well as integrated circuits.
A power module or power electronic module provides the physical containment for several power components, usually power semiconductor devices. These power semiconductors are typically soldered or sintered on a power electronic substrate that carries the power semiconductors, provides electrical and thermal contact and electrical insulation where needed. Compared to discrete power semiconductors in plastic housings as TO-247 or TO-220, power packages provide a higher power density and are in many cases more reliable.
Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages usually, but not always, include an exposed thermally conductive pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).
In electronics, TO-3 is a designation for a standardized metal semiconductor package used for power semiconductors, including transistors, silicon controlled rectifiers, and, integrated circuits. TO stands for "Transistor Outline" and relates to a series of technical drawings produced by JEDEC.
Metal electrode leadless face (MELF) is a type of leadless cylindrical electronic surface mount device that is metallized at its ends. MELF devices are usually diodes and resistors.
Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.
A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting it to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.
In electronics, a chip carrier is one of several kinds of surface-mount technology packages for integrated circuits. Connections are made on all four edges of a square package; compared to the internal cavity for mounting the integrated circuit, the package overall size is large.
A small outline transistor (SOT) is a family of small footprint, discrete surface mount transistor commonly used in consumer electronics. The most common SOT are SOT23 variations,. SOT23-5 differs from SOT23 in a wider body of 1.6 mm (0.063 in) instead of 1.3 mm (0.051 in). Also, manufacturers offer the nearly identical thin small outline transistor (TSOT/TSOP) package, where lower height is important.
The Thin Shrink Small Outline Package (TSSOP) is a rectangular surface mount plastic integrated circuit (IC) package with gull-wing leads.
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