Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow stacking and high-density packaging of integrated circuits (IC).
ICs are produced on semiconductor wafers that undergo a multitude of processing steps. The silicon wafers predominantly used today have diameters of 200 and 300 mm. They are roughly 750 μm thick to ensure a minimum of mechanical stability and to avoid warping during high-temperature processing steps.
Smartcards, USB memory sticks, smartphones, handheld music players, and other ultra-compact electronic products would not be feasible in their present form without minimizing the size of their various components along all dimensions. The backside of the wafers are thus ground prior to wafer dicing (separation of the individual microchips). Wafers thinned down to 75 to 50 μm are common today. [1]
Prior to grinding, wafers are commonly laminated with UV-curable back-grinding tape, which ensures against wafer surface damage during back-grinding and prevents wafer surface contamination caused by infiltration of grinding fluid and/or debris. [2] The wafers are also washed with deionized water throughout the process, which helps prevent contamination. [3]
The process is also known as "backlap", [4] "backfinish", "back side grinding", or "wafer thinning". [5]
After backgrinding, a finished wafer is cut into individual chips in a process called die singulation.
MEMS is the technology of microscopic devices incorporating both electronic and moving parts. MEMS are made up of components between 1 and 100 micrometres in size, and MEMS devices generally range in size from 20 micrometres to a millimetre, although components arranged in arrays can be more than 1000 mm2. They usually consist of a central unit that processes data and several components that interact with the surroundings.
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips that are present in everyday electrical and electronic devices. It is a multiple-step photolithographic and physio-chemical process during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
In electronics, a wafer is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells.
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Department, Utica, New York. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and fine wires are welded onto the chip pads and lead frame contacts to interconnect the chip pads to external circuitry.
Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation typically consists of two steps: wafer mounting and wafer dicing.
Chemical mechanical polishing (CMP) is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing. It is used in the semiconductor industry to polish semiconductor wafers as part of the integrated circuit manufacturing process.
Deep reactive-ion etching (DRIE) is a highly anisotropic etch process used to create deep penetration, steep-sided holes and trenches in wafers/substrates, typically with high aspect ratios. It was developed for microelectromechanical systems (MEMS), which require these features, but is also used to excavate trenches for high-density capacitors for DRAM and more recently for creating through silicon vias (TSVs) in advanced 3D wafer level packaging technology. In DRIE, the substrate is placed inside a reactor, and several gases are introduced. A plasma is struck in the gas mixture which breaks the gas molecules into ions. The ions accelerated towards, and react with the surface of the material being etched, forming another gaseous element. This is known as the chemical part of the reactive ion etching. There is also a physical part, if ions have enough energy, they can knock atoms out of the material to be etched without chemical reaction.
Microfabrication is the process of fabricating miniature structures of micrometre scales and smaller. Historically, the earliest microfabrication processes were used for integrated circuit fabrication, also known as "semiconductor manufacturing" or "semiconductor device fabrication". In the last two decades microelectromechanical systems (MEMS), microsystems, micromachines and their subfields, microfluidics/lab-on-a-chip, optical MEMS, RF MEMS, PowerMEMS, BioMEMS and their extension into nanoscale have re-used, adapted or extended microfabrication methods. Flat-panel displays and solar cells are also using similar techniques.
Die singulation, also called wafer dicing, is the process in semiconductor device fabrication by which dies are separated from a finished wafer of semiconductor. Die singulation comes after the photolithography process. It can involve scribing and breaking, mechanical sawing or laser cutting. All methods are typically automated to ensure precision and accuracy. Following the dicing process the individual silicon chips may be encapsulated into chip carriers which are then suitable for use in building electronic devices such as computers, etc.
The RCA clean is a standard set of wafer cleaning steps which need to be performed before high-temperature processing steps of silicon wafers in semiconductor manufacturing.
In semiconductor electronics fabrication technology, a self-aligned gate is a transistor manufacturing approach whereby the gate electrode of a MOSFET is used as a mask for the doping of the source and drain regions. This technique ensures that the gate is naturally and precisely aligned to the edges of the source and drain.
Etching is used in microfabrication to chemically remove layers from the surface of a wafer during manufacturing. Etching is a critically important process module in fabrication, and every wafer undergoes many etching steps before it is complete.
ASM is a Dutch headquartered multinational corporation that specializes in the design, manufacturing, sales and service of semiconductor wafer processing equipment for the fabrication of semiconductor devices. ASM's products are used by semiconductor manufacturers in front-end wafer processing in their semiconductor fabrication plants. ASM’s technologies include atomic layer deposition, epitaxy, chemical vapor deposition and diffusion.
Monocrystalline silicon, more often called single-crystal silicon, in short mono c-Si or mono-Si, is the base material for silicon-based discrete components and integrated circuits used in virtually all modern electronic equipment. Mono-Si also serves as a photovoltaic, light-absorbing material in the manufacture of solar cells.
A back-illuminated sensor, also known as backside illumination (BI) sensor, is a type of digital image sensor that uses a novel arrangement of the imaging elements to increase the amount of light captured and thereby improve low-light performance.
Ultra-high-purity steam, also called the clean steam, UHP steam or high purity water vapor, is used in a variety of industrial manufacturing processes that require oxidation or annealing. These processes include the growth of oxide layers on silicon wafers for the semiconductor industry, originally described by the Deal-Grove model, and for the formation of passivation layers used to improve the light capture ability of crystalline photovoltaic cells. Several methods and technologies can be employed to generate ultra high purity steam, including pyrolysis, bubbling, direct liquid injection, and purified steam generation. The level of purity, or the relative lack of contamination, affects the quality of the oxide layer or annealed surface. The method of delivery affects growth rate, uniformity, and electrical performance. Oxidation and annealing are common steps in the manufacture of such devices as microelectronics and solar cells.
Anodic bonding is a wafer bonding process to seal glass to either silicon or metal without introducing an intermediate layer; it is commonly used to seal glass to silicon wafers in electronics and microfluidics. This bonding technique, also known as field assisted bonding or electrostatic sealing, is mostly used for connecting silicon/glass and metal/glass through electric fields. The requirements for anodic bonding are clean and even wafer surfaces and atomic contact between the bonding substrates through a sufficiently powerful electrostatic field. Also necessary is the use of borosilicate glass containing a high concentration of alkali ions. The coefficient of thermal expansion (CTE) of the processed glass needs to be similar to those of the bonding partner.
Eutectic bonding, also referred to as eutectic soldering, describes a wafer bonding technique with an intermediate metal layer that can produce a eutectic system. Those eutectic metals are alloys that transform directly from solid to liquid state, or vice versa from liquid to solid state, at a specific composition and temperature without passing a two-phase equilibrium, i.e. liquid and solid state. The fact that the eutectic temperature can be much lower than the melting temperature of the two or more pure elements can be important in eutectic bonding.
Glass frit bonding, also referred to as glass soldering or seal glass bonding, describes a wafer bonding technique with an intermediate glass layer. It is a widely used encapsulation technology for surface micro-machined structures, e.g., accelerometers or gyroscopes. This technique utilizes low melting-point glass and therefore provides various advantages including that viscosity of glass decreases with an increase of temperature. The viscous flow of glass has effects to compensate and planarize surface irregularities, convenient for bonding wafers with a high roughness due to plasma etching or deposition. A low viscosity promotes hermetically sealed encapsulation of structures based on a better adaption of the structured shapes. Further, the coefficient of thermal expansion (CTE) of the glass material is adapted to silicon. This results in low stress in the bonded wafer pair. The glass has to flow and wet the soldered surfaces well below the temperature where deformation or degradation of either of the joined materials or nearby structures occurs. The usual temperature of achieving flowing and wetting is between 450 and 550 °C.
Glossary of microelectronics manufacturing terms