Planar process

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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed [1] [2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor, with a first patent issued 1959.


Annotated die photo of a Fairchild chip

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using near-ultraviolet light from a mercury vapor lamp. As of 2011, small features are typically made with 193 nm "deep" UV lithography. [3] Some researchers use even higher-energy extreme ultraviolet lithography.

See also


  1. US 3025589 Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. US 3064167 Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).