Process variation (semiconductor)

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Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness) when integrated circuits are fabricated. [1] The amount of process variation becomes particularly pronounced at smaller process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the device and as feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for patterning lithography masks.

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Semiconductor device fabrication process used to create the integrated circuits that are present in everyday electrical and electronic devices

Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

The term die shrink refers to a simple semiconductor scaling of semiconductor devices, mainly transistors. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, usually involving an advance of lithographic node. This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs, while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold.

Contents

Process variation causes measurable and predictable variance in the output performance of all circuits but particularly analog circuits due to mismatch. [2] If the variance causes the measured or simulated performance of a particular output metric (bandwidth, gain, rise time, etc.) to fall below or rise above the specification for the particular circuit or device, it reduces the overall yield for that set of devices.

History

The first mention of variation in semiconductors was by William Shockley, the co-inventor of the transistor, in his 1961 analysis of junction breakdown. [3]

William Shockley American physicist and inventor

William Bradford Shockley Jr. was an American physicist and inventor. Shockley was the manager of a research group at Bell Labs that included John Bardeen and Walter Brattain. The three scientists were jointly awarded the 1956 Nobel Prize in Physics for "their researches on semiconductors and their discovery of the transistor effect".

An analysis of systematic variation was performed by Schemmert and Zimmer in 1974 with their paper on threshold-voltage sensitivity. [4] This research looked into the effect that the oxide thickness and implantation energy had on the threshold voltage of MOS devices.

Threshold voltage Minimum source-to-gate voltage for a field effect transistor to be conducting from source to drain

The threshold voltage, commonly abbreviated as Vth, of a field-effect transistor (FET) is the minimum gate-to-source voltage VGS (th) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.

sources of variations 1) gate oxide thickness 2) random dopant fluctuations 3) Device Geometry, Lithography in nanometer region

Characterization

Semiconductor foundries run analyses on the variability of attributes of transistors (length, width, oxide thickness, etc.) for each new process node. These measurements are recorded and provided to customers such as fabless semiconductor companies. This set of files are generally referred to as "model files" in the industry and are used by EDA tools for simulation of designs.

FEOL

Typically process models (example HSPICE ) include process corners based on Front End Of Line conditions. These often are centered at a typical or nominal point and will also contain Fast and Slow corners often separated into Ntype and Ptype corners that affect the non-linear active N+ / P+ devices in different ways. Examples are TT for nominal N+ and P+ transistors, FF for fast N+ and P+ transistors, FS for fast N+ and slow P+ transistors, etc.

In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin.

Front end of line

The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices are patterned in the semiconductor. FEOL generally covers everything up to the deposition of metal interconnect layers.

BEOL

When modeling the parasitic wiring an orthogonal set of process corners is often supplied with the parasitic extraction deck. (Example STAR-RC extraction deck) These corners are usually listed as Typical/Nominal for the target value and Cbest / Cworst corners for the variations in: conductor thickness, conductor width, and conductor oxide thickness that result in the Least / Most capacitance on the wiring. Often an additional corner called RCbest and RCworst is supplied that picks the conductor parameters that result in the Best (lowest) and worst (highest) wiring resistance for thickness and width, and then adds the oxide thicksness that adds the Best (lowest) and Worst (highest) capacitance due to the oxide thickness as this value is not directly correlated to wiring resistance.

Workarounds & Solutions

Statistical Analysis

Designers using this approach run from tens to thousands of simulations to analyze how the outputs of the circuit will behave according to the measured variability of the transistors for that particular process. The measured criteria for transistors are recorded in model files given to designers for simulating their circuits before simulation.

The most basic approach used by designers is increasing the size of devices which are sensitive to mismatch.

Topology Optimization

This is used to reduce variation due to polishing, etc. [5]

Patterning Techniques

To reduce roughness of line edges, advanced lithography techniques are used.

See also

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References

  1. ↑ "A Survey Of Architectural Techniques for Managing Process Variation", ACM Computing Surveys, 2015
  2. ↑ Patrick Drennan, "Understanding MOSFET Mismatch for Analog Design" IEEE Journal of Solid-State Circuits, Vol 38, No 3, March 2003
  3. ↑ W. Shockley, “Problems related to p-n junctions in silicon.” Solid-State Electronics, Volume 2, January 1961, pp. 35–67.
  4. ↑ W. Schemmert, G. Zimmer, "Threshold-voltage sensitivity of ion-implanted m.o.s.transistors due to process variations." Electronics Letters, Volume 10, Issue 9, May 2, 1974, pp. 151-152
  5. ↑ "Managing Process Variation in Intel's 45nm CMOS Technology." Intel Technology Journal, Volume 12, Issue 2 June 17, 2008 http://www.intel.com/technology/itj/2008/v12i2/3-managing/1-abstract.htm
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