Through-silicon via

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TSVs used by stacked DRAM-dice in combination with a High Bandwidth Memory interface High Bandwidth Memory schematic.svg
TSVs used by stacked DRAM-dice in combination with a High Bandwidth Memory interface

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

Electronic engineering electrical engineering discipline which utilizes nonlinear and active electrical components to design electronic circuits, devices, and their systems

Electronic engineering is an electrical engineering discipline which utilizes nonlinear and active electrical components to design electronic circuits, devices, VLSI devices and their systems. The discipline typically also designs passive electrical components, usually based on printed circuit boards.

A via or VIA is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. To ensure via robustness, IPC sponsored a round-robin exercise that developed a time to failure calculator.

Die (integrated circuit) an unpackaged integrated circuit

A die, in the context of integrated circuits, is a small block of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor through processes such as photolithography. The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a die.



Visualizing via-first, via-middle and via-last TSVs Through-Silicon Via Flavours.svg
Visualizing via-first, via-middle and via-last TSVs

Dictated by the manufacturing process, there exist three different types of TSVs: via-first TSVs are fabricated before the individual devices (transistors, capacitors, resistors, etc.) are patterned (front end of line, FEOL), via-middle TSVs are fabricated after the individual devices are patterned but before the metal layers (back-end-of-line, BEOL), and via-last TSVs are fabricated after (or during) the BEOL process. [1] [2] Via-middle TSVs are currently a popular option for advanced 3D ICs as well as for interposer stacks. [2] [3]

Transistor semiconductor device used to amplify and switch electronic signals and electrical power

A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits.

Capacitor electrical component used to store energy for a short period of time

A capacitor is a passive two-terminal electronic component that stores electrical energy in an electric field. The effect of a capacitor is known as capacitance. While some capacitance exists between any two electrical conductors in proximity in a circuit, a capacitor is a component designed to add capacitance to a circuit. The capacitor was originally known as a condenser or condensator. The original name is still widely used in many languages, but not commonly in English.

Resistor Passive electrical component providing electrical resistance

A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. In electronic circuits, resistors are used to reduce current flow, adjust signal levels, to divide voltages, bias active elements, and terminate transmission lines, among other uses. High-power resistors that can dissipate many watts of electrical power as heat, may be used as part of motor controls, in power distribution systems, or as test loads for generators. Fixed resistors have resistances that only change slightly with temperature, time or operating voltage. Variable resistors can be used to adjust circuit elements, or as sensing devices for heat, light, humidity, force, or chemical activity.

TSVs through the front end of line (FEOL) have to be carefully accounted for during the EDA and manufacturing phases. That is because TSVs induce thermo-mechanical stress in the FEOL layer, thereby impacting the transistor behaviour. [4]

Front end of line

The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices are patterned in the semiconductor. FEOL generally covers everything up to the deposition of metal interconnect layers.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design.

Stress (mechanics) physical quantity that expresses internal forces in a continuous material

In continuum mechanics, stress is a physical quantity that expresses the internal forces that neighbouring particles of a continuous material exert on each other, while strain is the measure of the deformation of the material. For example, when a solid vertical bar is supporting an overhead weight, each particle in the bar pushes on the particles immediately below it. When a liquid is in a closed container under pressure, each particle gets pushed against by all the surrounding particles. The container walls and the pressure-inducing surface push against them in (Newtonian) reaction. These macroscopic forces are actually the net result of a very large number of intermolecular forces and collisions between the particles in those molecules. Stress is frequently represented by a lowercase Greek letter sigma (σ).


Image sensors

CMOS image sensors (CIS) were among the first applications to adopt TSV(s) in volume manufacturing. In initial CIS applications, TSVs were formed on the backside of the image sensor wafer to form interconnects, eliminate wire bonds, and allow for reduced form factor and higher-density interconnects. Chip stacking came about only with the advent of backside illuminated (BSI) CIS, and involved reversing the order of the lens, circuitry, and photodiode from traditional front-side illumination so that the light coming through the lens first hits the photodiode and then the circuitry. This was accomplished by flipping the photodiode wafer, thinning the backside, and then bonding it on top of the readout layer using a direct oxide bond, with TSVs as interconnects around the perimeter. [5]

Back-illuminated sensor

A back-illuminated sensor, also known as backside illumination sensor, is a type of digital image sensor that uses a novel arrangement of the imaging elements to increase the amount of light captured and thereby improve low-light performance.

3D packages

A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package can be found in IBM's Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, TSVs replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).

A system in package (SiP) or system-in-a-package is a number of integrated circuits enclosed in a single chip carrier package. The SiP performs all or most of the functions of an electronic system, and is typically used inside a mobile phone, digital music player, etc. Dies containing integrated circuits may be stacked vertically on a substrate. They are internally connected by fine wires that are bonded to the package. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together. Systems-in-package are like systems-on-chip (SoC) but less tightly integrated and not on a single semiconductor die.


An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.

3D integrated circuits

A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.” The different devices in the stack may be heterogeneous, e.g. combining CMOS logic, DRAM and III-V materials into a single IC. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation. The Wide I/O 3D DRAM memory standard (JEDEC JESD229) includes TSV in the design. [6]

JEDEC standards organization

The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body.

History of the term

The first TSV was patented by William Shockley in 1962, [7] although most people in the electronics industry consider Merlin Smith and Emanuel Stern of IBM the inventors of TSV, based on their patent “Methods of Making Thru-Connections in Semiconductor Wafers” filed on December 28, 1964 and granted on September 26, 1967.

However, it wasn't until the late 1990s that the term "Through Silicon Via" was coined by Dr. Sergey Savastiouk, the co-founder and current CEO of ALLVIA Inc. as part of his original business plan. From the beginning, the vision of the business plan was to create a through silicon interconnect since these would offer significant performance improvements over wire bonds. Savastiouk published two articles on the topic in Solid State Technology, first in January 2000 and again in 2010. The first article “Moore’s Law – The Z Dimension” was published in Solid State Technology magazine in January 2000. [8] This article outlined the roadmap of the TSV development as a transition from 2D chip stacking to wafer level stacking in the future. In one of the sections titled Through Silicon Vias, Dr. Sergey Savastiouk wrote, “Investment in technologies that provide both wafer-level vertical miniaturization (wafer thinning) and preparation for vertical integration (through silicon vias) makes good sense.” He continued, “By removing the arbitrary 2D conceptual barrier associated with Moore’s Law, we can open up a new dimension in ease of design, test, and manufacturing of IC packages. When we need it the most – for portable computing, memory cards, smart cards, cellular phones, and other uses – we can follow Moore’s Law into the Z dimension.” This was the first time the term "through-silicon via" was used in a technical publication.

Related Research Articles

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon 639-1 ısoo

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny transistors into a small chip results in circuits that are orders of magnitude smaller, cheaper, and faster than those constructed of discrete electronic components. The IC's mass production capability, reliability and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Semiconductor device fabrication process used to create the integrated circuits that are present in everyday electrical and electronic devices

Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Photodiode type of photodetector based on a p-n-junction

A photodiode is a semiconductor device that converts light into an electrical current. The current is generated when photons are absorbed in the photodiode. Photodiodes may contain optical filters, built-in lenses, and may have large or small surface areas. Photodiodes usually have a slower response time as their surface area increases. The common, traditional solar cell used to generate electric solar power is a large area photodiode.

Chip-scale package

A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.

Back end of line

The back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring on the wafer, the metalization layer. Common metals are copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

Multi-chip module

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it is treated as if it were a single component . Other terms, such as "hybrid" or "hybrid integrated circuit", also refer to MCMs.

Memory module

In computing, a memory module is a printed circuit board on which memory integrated circuits are mounted. Memory modules permit easy installation and replacement in electronic systems, especially computers such as personal computers, workstations, and servers. The first memory modules were proprietary designs that were specific to a model of computer from a specific manufacturer. Later, memory modules were standardized by organizations such as JEDEC and could be used in any system designed to use them.

In microelectronics, a three-dimensional integrated circuit is an integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. 3D IC is just one of a host of 3D integration schemes that exploit the z-direction to achieve electrical performance benefits.

In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin.

Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth interface.

Integrated passive devices

Integrated Passive Devices (IPD's) "or Integrated Passive Components (IPC's)" are attracting an increasing interest due to constant needs of handheld wireless devices to further decrease in size and cost and increase in functionality.

Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow stacking and high-density packaging of integrated circuits (IC).

Embedded Wafer Level Ball Grid Array

Embedded Wafer Level Ball Grid Array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.

Hybrid Memory Cube (HMC) is a high-performance RAM interface for through-silicon vias (TSV)-based stacked DRAM memory competing with the incompatible rival interface High Bandwidth Memory (HBM).

High Bandwidth Memory high-performance RAM interface for 3D-stacked DRAM from AMD and Hynix

High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked DRAM from Samsung, AMD and Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices. The first devices to use HBM are the AMD Fiji GPUs.

In computing, a logic block or configurable logic block (CLB) is a fundamental building block of field-programmable gate array (FPGA) technology. Logic blocks can be configured by the engineer to provide reconfigurable logic gates.

In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and fabrication yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the semiconductor substrate, and the dielectric in between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication, interconnects are formed during the back-end-of-line after the fabrication of the transistors on the substrate.


  1. "International Technology Roadmap for Semiconductors. 2009 edition. Interconnect" (PDF). 2009. pp. 4–5. Retrieved 2 January 2018.
  2. 1 2 J. Knechtel; et al. (2017). "Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration". IPSJ Transactions on System LSI Design Methodology. 10: 45–62. doi:10.2197/ipsjtsldm.10.45.CS1 maint: Explicit use of et al. (link)
  3. Beyne, E. (June 2016). "The 3-D Interconnect Technology Landscape". IEEE Design Test. 33 (3): 8–20. doi:10.1109/mdat.2016.2544837. ISSN   2168-2356.
  4. Lim, S.K. (2013). Design for High Performance, Low Power, and Reliable 3D Integrated Circuits - Springer. doi:10.1007/978-1-4419-9542-1. ISBN   978-1-4419-9541-4.
  5. F. von Trapp, The Future Of Image Sensors is Chip Stacking
  6. Desjardins, E. "JEDEC Publishes Breakthrough Standard for Wide I/O Mobile DRAM". JEDEC. JEDEC. Retrieved 1 December 2014.
  7. J.H. Lau, Who Invented the Through Silicon Via (TSV) and When? 3D InCites, 2010,
  8. AUTHOR(S)Savastiouk, Sergey, Moore's Law in the Z-Direction, Solid State Technology; Jan 2000, Vol. 43 Issue 1, p84