Hybrid Memory Cube

Last updated

Hybrid Memory Cube (HMC) is a high-performance computer random-access memory (RAM) interface for through-silicon via (TSV)-based stacked DRAM memory. HMC competes with the incompatible rival interface High Bandwidth Memory (HBM).

Contents

Overview

Hybrid Memory Cube was co-developed by Samsung Electronics and Micron Technology in 2011, [1] and announced by Micron in September 2011. [2] It promised a 15 times speed improvement over DDR3. [3] The Hybrid Memory Cube Consortium (HMCC) is backed by several major technology companies including Samsung, Micron Technology, Open-Silicon, ARM, HP (since withdrawn), Microsoft (since withdrawn), Altera (acquired by Intel in late 2015), and Xilinx. [4] [5] Micron, while continuing to support HMCC, is discontinuing the HMC product [6] in 2018 when it failed to achieve market adoption.

HMC combines through-silicon vias (TSV) and microbumps to connect multiple (currently 4 to 8) dies of memory cell arrays on top of each other. [7] The memory controller is integrated as a separate die. [2]

HMC uses standard DRAM cells but it has more data banks than classic DRAM memory of the same size. The HMC interface is incompatible with current DDRn (DDR2 or DDR3) and competing High Bandwidth Memory implementations. [8]

HMC technology won the Best New Technology award from The Linley Group (publisher of Microprocessor Report magazine) in 2011. [9] [10]

The first public specification, HMC 1.0, was published in April 2013. [11] According to it, the HMC uses 16-lane or 8-lane (half size) full-duplex differential serial links, with each lane having 10, 12.5 or 15 Gbit/s SerDes. [12] Each HMC package is named a cube, and they can be chained in a network of up to 8 cubes with cube-to-cube links and some cubes using their links as pass-through links. [13] A typical cube package with 4 links has 896 BGA pins and a size of 31×31×3.8 millimeters. [14]

The typical raw bandwidth of a single 16-lane link with 10 Gbit/s signalling implies a total bandwidth of all 16 lanes of 40 GB/s (20 GB/s transmit and 20 GB/s receive); cubes with 4 and 8 links are planned, though the HMC 1.0 spec limits link speed to 10 Gbit/s in the 8-link case. Therefore, a 4-link cube can reach 240 GB/s memory bandwidth (120 GB/s each direction using 15 Gbit/s SerDes), while an 8-link cube can reach 320 GB/s bandwidth (160 GB/s each direction using 10 Gbit/s SerDes). [15] Effective memory bandwidth utilization varies from 33% to 50% for smallest packets of 32 bytes; and from 45% to 85% for 128 byte packets. [7]

As reported at the HotChips 23 conference in 2011, the first generation of HMC demonstration cubes with four 50 nm DRAM memory dies and one 90 nm logic die with total capacity of 512 MB and size 27×27 mm had power consumption of 11 W and was powered with 1.2 V. [7]

Engineering samples of second generation HMC memory chips were shipped in September 2013 by Micron. [3] Samples of 2 GB HMC (stack of 4 memory dies, each of 4 Gbit) are packed in a 31×31 mm package and have 4 HMC links. Other samples from 2013 have only two HMC links and a smaller package: 16×19.5 mm. [16]

The second version of the HMC specification was published on 18 November 2014 by HMCC. [17] HMC2 offers a variety of SerDes rates ranging from 12.5 Gbit/s to 30 Gbit/s, yielding an aggregate link bandwidth of 480 GB/s (240 GB/s each direction), though promising only a total DRAM bandwidth of 320 GB/sec. [18] A package may have either 2 or 4 links (down from the 4 or 8 in HMC1), and a quarter-width option is added using 4 lanes.

The first processor to use HMCs was the Fujitsu SPARC64 XIfx, [19] which is used in the Fujitsu PRIMEHPC FX100 supercomputer introduced in 2015.

JEDEC's Wide I/O and Wide I/O 2 are seen as the mobile computing counterparts to the desktop/server-oriented HMC in that both involve 3D die stacks. [20]

In August 2018, Micron announced a move away from HMC to pursue competing high-performance memory technologies such as GDDR6 and HBM. [21]

See also

Related Research Articles

<span class="mw-page-title-main">Synchronous dynamic random-access memory</span> Type of computer memory

Synchronous dynamic random-access memory is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.

HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001. The HyperTransport Consortium is in charge of promoting and developing HyperTransport technology.

Double Data Rate 3 Synchronous Dynamic Random-Access Memory is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.

<span class="mw-page-title-main">Multi-chip module</span> Electronic assembly containing multiple integrated circuits that behaves as a unit

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

GDDR4 SDRAM, an abbreviation for Graphics Double Data Rate 4 Synchronous Dynamic Random-Access Memory, is a type of graphics card memory (SGRAM) specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM. GDDR4 is based on DDR3 SDRAM technology and was intended to replace the DDR2-based GDDR3, but it ended up being replaced by GDDR5 within a year.

<span class="mw-page-title-main">GDDR5 SDRAM</span> Type of high performance DRAM graphics card memory

Graphics Double Data Rate 5 Synchronous Dynamic Random-Access Memory is a type of synchronous graphics random-access memory (SGRAM) with a high bandwidth interface designed for use in graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM.

<span class="mw-page-title-main">Solid-state drive</span> Computer storage device with no moving parts

A solid-state drive (SSD) is a solid-state storage device. It provides persistent data storage using no moving parts. It is sometimes called semiconductor storage device or solid-state device. It is also called solid-state disk because it is frequently interfaced to a host system in the same manner as a hard disk drive (HDD).

<span class="mw-page-title-main">Through-silicon via</span> Electrical connection

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

Double Data Rate 4 Synchronous Dynamic Random-Access Memory is a type of synchronous dynamic random-access memory with a high bandwidth interface.

<span class="mw-page-title-main">LPDDR</span> Computer hardware

Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known as Mobile DDR, and abbreviated as mDDR.

Terabit Ethernet (TbE) is Ethernet with speeds above 100 Gigabit Ethernet. The 400 Gigabit Ethernet and 200 Gigabit Ethernet standard developed by the IEEE P802.3bs Task Force using broadly similar technology to 100 Gigabit Ethernet was approved on December 6, 2017. On February 16, 2024 the 800 Gigabit Ethernet standard developed by the IEEE P802.3df Task Force was approved.

<span class="mw-page-title-main">DDR5 SDRAM</span> Fifth generation of double-data-rate synchronous dynamic random-access memory

Double Data Rate 5 Synchronous Dynamic Random-Access Memory is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on July 14, 2020.

<span class="mw-page-title-main">High Bandwidth Memory</span> Type of memory used on processors that require high transfer rate memory

High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI ASICs, as on-package cache in CPUs and on-package RAM in upcoming CPUs, and FPGAs and in some supercomputers. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015.

<span class="mw-page-title-main">3D XPoint</span> Discontinued computer memory type

3D XPoint is a discontinued non-volatile memory (NVM) technology developed jointly by Intel and Micron Technology. It was announced in July 2015 and was available on the open market under the brand name Optane (Intel) from April 2017 to July 2022. Bit storage is based on a change of bulk resistance, in conjunction with a stackable cross-grid data access array, using a phenomenon known as Ovonic Threshold Switch (OTS). Initial prices are less than dynamic random-access memory (DRAM) but more than flash memory.

Multi-Channel DRAM or MCDRAM is a 3D-stacked DRAM that is used in the Intel Xeon Phi processor codenamed Knights Landing. It is a version of Hybrid Memory Cube developed in partnership with Micron Technology, and a competitor to High Bandwidth Memory.

Coherent Accelerator Processor Interface (CAPI), is a high-speed processor expansion bus standard for use in large data center computers, initially designed to be layered on top of PCI Express, for directly connecting central processing units (CPUs) to external accelerators like graphics processing units (GPUs), ASICs, FPGAs or fast storage. It offers low latency, high speed, direct memory access connectivity between devices of different instruction set architectures.

Graphics Double Data Rate 6 Synchronous Dynamic Random-Access Memory is a type of synchronous graphics random-access memory (SGRAM) with a high bandwidth, "double data rate" interface, designed for use in graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM, and is the successor to GDDR5. Just like GDDR5X it uses QDR in reference to the write command clock (WCK) and ODR in reference to the command clock (CK).

Graphics Double Data Rate 7 Synchronous Dynamic Random-Access Memory is a type of synchronous graphics random-access memory (SGRAM) specified by the JEDEC Semiconductor Memory Standard, with a high bandwidth, "double data rate" interface, designed for use in graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM, and is the successor to GDDR6.

References

  1. ↑ Kada, Morihiro (2015). "Research and Development History of Three-Dimensional Integration Technology" (PDF). Three-Dimensional Integration of Semiconductors: Processing, Materials, and Applications. Springer. pp. 15–6. ISBN   9783319186757. Archived from the original (PDF) on 23 October 2021. Retrieved 19 July 2019.
  2. 1 2 Micron Reinvents DRAM Memory, Linley Group, Jag Bolaria, 12 September 2011
  3. 1 2 Mearian, Lucas (25 September 2013). "Micron ships Hybrid Memory Cube that boosts DRAM 15X". computerworld.com. Computerworld. Archived from the original on 11 October 2014. Retrieved 4 November 2014.
  4. ↑ Microsoft backs Hybrid Memory Cube tech // by Gareth Halfacree, bit-tech, 9 May 2012
  5. ↑ "About Us". Hybrid Memory Cube Consortium. Archived from the original on 10 October 2011. Retrieved 10 October 2011.
  6. ↑ "FAQs". www.micron.com. Retrieved 5 December 2018.
  7. 1 2 3 Hybrid Memory Cube (HMC), J. Thomas Pawlowski (Micron) // HotChips 23
  8. ↑ Memory for Exascale and ... Micron's new memory component is called HMC: Hybrid Memory Cube Archived 17 April 2012 at the Wayback Machine by Dave Resnick (Sandia National Laboratories) // 2011 Workshop on Architectures I: Exascale and Beyond, 8 July 2011
  9. ↑ Micron's Hybrid Memory Cubes win tech award // by Gareth Halfacree, bit-tech, 27 January 2012
  10. ↑ Best Processor Technology of 2011 // The Linley Group, Tom Halfhill, 23 Jan 2012
  11. ↑ Hybrid Memory Cube receives its finished spec, promises up to 320 GB per second By Jon Fingas // Engadget, 3 April 2013
  12. ↑ HMC 1.0 Specification, Chapter "1 HMC Architecture"
  13. ↑ HMC 1.0 Specification, Chapter "5 Chaining"
  14. ↑ HMC 1.0 Specification, Chapter "19 Packages for HMC-15G-SR Devices"
  15. ↑ "Hybrid Memory Cube Specification 1.0" (PDF). HMC Consortium. 1 January 2013. Archived from the original (PDF) on 13 May 2013. Retrieved 10 August 2016.
  16. ↑ Hruska, Joel (25 September 2013). "Hybrid Memory Cube 160GB/sec RAM starts shipping: Is this the technology that finally kills DDR RAM?". Extremetech. Extreme Tech. Retrieved 27 September 2013.
  17. ↑ Hybrid Memory Cube Consortium Advances Hybrid Memory Cube Performance and Industry Adoption With Release of New Specification Archived 1 August 2016 at the Wayback Machine , 18 November 2014
  18. ↑ "Hybrid Memory Cube Specification 2.1" (PDF). HMC Consortium. 5 November 2015. Archived from the original (PDF) on 9 January 2016. Retrieved 10 August 2016.
  19. ↑ Halfhill, Tom R. (22 September 2014). "Sparc64 XIfx Uses Memory Cubes". Microprocessor Report .
  20. ↑ Goering, Richard (6 August 2013). "Wide I/O 2, Hybrid Memory Cube (HMC) – Memory Models Advance 3D-IC Standards". cadence.com. Cadence Design Systems . Retrieved 8 December 2014.
  21. ↑ "Micron Announces Shift in High-Performance Memory Roadmap Strategy".
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.