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Double Data Rate 2 Synchronous Dynamic Random-Access Memory
Type of RAM
Swissbit 2GB PC2-5300U-555.jpg
Front and back of a 2GB PC2-5300 DDR2 RAM module for desktop PCs (DIMM)
Developer JEDEC
Type Synchronous dynamic random-access memory
Generation2nd generation
Release date2003 (2003)
  • DDR2-400 (PC2-3200)
  • DDR2-533 (PC2-4266)
  • DDR2-666 (PC2-5333)
  • DDR2-800 (PC2-6400)
  • DDR2-1066 (PC2-8533)
Clock rate 100-266.⅔ MHz
Cycle time10-3.75 ns
Bus clock rate200-533.⅓ MHz
Transfer rate 400-1066.⅔ MT/s
Voltage 1.8 V
PC2-5300 DDR2 SO-DIMM (for notebooks) Samsung-1GB-DDR2-Laptop-RAM.jpg
PC2-5300 DDR2 SO-DIMM (for notebooks)

Double Data Rate 2 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR2 SDRAM, is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by DDR3 SDRAM (launched in 2007). DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.

Double data rate

In computing, a computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used in the context of NAND flash memory.

Synchronous dynamic random-access memory (SDRAM) is any dynamic random-access memory (DRAM) where the operation of its external pin interface is coordinated by an externally supplied clock signal. DRAM integrated circuits (ICs) produced from the early 1970s to mid-1990s used an asynchronous interface, in which input control signals have a direct effect on internal functions only delayed by the trip across its semiconductor pathways. SDRAM has a synchronous interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called banks, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an interleaved fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

An external memory interface is a bus protocol for communication from an integrated circuit, such as a microprocessor, to an external memory device located on a circuit board. The memory is referred to as external because it is not contained within the internal circuitry of the integrated circuit and thus is externally located on the circuit board.


In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.

Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same bandwidth but with higher latency. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.

Memory timings or RAM timings describe the performance of synchronous dynamic random-access memory (SDRAM) using four parameters: CL, TRCD, TRP, and TRAS in units of clock cycles; they are commonly written as four numbers separated with dashes, e.g. 7-8-8-24. The fourth (tRAS) is often omitted, or a fifth, the Command rate, sometimes added. These parameters specify the latencies that affect speed of random access memory. Lower numbers usually imply faster performance. What determines absolute system performance is actual latency time, usually measured in nanoseconds.


Comparison of memory modules for desktop PCs (DIMM). Desktop DDR Memory Comparison.svg
Comparison of memory modules for desktop PCs (DIMM).
Comparison of memory modules for portable/mobile PCs (SO-DIMM). Laptop SODIMM DDR Memory Comparison V2.svg
Comparison of memory modules for portable/mobile PCs (SO-DIMM).

The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length was two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits were read or written to or from a four-bit-deep prefetch queue. This queue received or transmitted its data over the data bus in two data bus clock cycles (each clock cycle transferred two bits of data. Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data could be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array could be accessed. DDR2 SDRAM was designed with such a scheme to avoid an excessive increase in power consumption.

DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is four bits deep, whereas it is two bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

On-die termination (ODT) is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board (PCB).

In computing, memory latency is the time between initiating a request for a byte or word in memory until it is retrieved by a processor. If the data are not in the processor's cache, it takes longer to obtain them, as the processor will have to communicate with the external memory cells. Latency is therefore a fundamental measure of the speed of memory: the less the latency, the faster the reading operation.

Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bus speeds.

Ball grid array

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.


Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate synchronous dynamic random-access memory class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, and DDR4 memory modules will not work in DDR1-equipped motherboards, and vice versa.

Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

According to JEDEC [1] the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).

Specification standards

Chips and modules

For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins and often come identified by an additional S in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth).

Comparison of DDR2 SDRAM standards
Name Chip Bus Timings Voltage
StandardTypeModule Clock rate (MHz)Cycle time (ns) Prefetch Clock rate (MHz) Transfer rate (MT/s) Bandwidth (MB/s)CL-TRCD-TRP [2] [3] CAS latency (ns)
DDR2-400BPC2-3200100104 bits20040032003-3-3151.8 V

Relative speed comparison between similar modules

PC2-3200 4-4-4%%+33%+60%%
PC2-3200 3-3-3%%=+20%%
PC2-4200 4-4-4%%=+21%%
PC2-4200 3-3-3%%−24%−9%%
PC2-5300 5-5-5%%=+21%%
PC2-5300 4-4-4%%−19%−3%%
PC2-6400 6-6-6%%=+20%%
PC2-6400 5-5-5%%−16%=%
PC2-6400 4-4-4%%−33%−20%%
PC2-8500 7-7-7%%−12%+6%%
PC2-8500 6-6-6%%−25%−9%%

*Some manufacturers label their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the respective names suggested by JEDEC. At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate [4] whilst others simply round up for the name.

Note: DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

DDR2 P vs F Server DIMM's Notch Positions compared. DDR2 F 'Fully Buffer' vs 'Parity' notch position.jpg
DDR2 P vs FServer DIMM's Notch Positions compared.

In addition to bandwidth and capacity variants, modules can:

  1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC. An additional P can be added at the end of the designation, P standing for parity (ex : PC2-5300P).
  2. Intel (r) 6402 Advanced Memory Buffer Intel (r) 6402 Advanced Memory Buffer..jpg
    Intel ® 6402 Advanced Memory Buffer
    Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
  3. Be aware fully buffered modules, which are designated by F or FB do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.



DDR2 was introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance. DDR2 started to become competitive against the older DDR standard by the end of 2004, as modules with lower latencies became available. [5]

Backward compatibility

DDR2 DIMMs are not backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin SO-DIMMs for DDR and DDR2; however, the notch on DDR2 modules is in a slightly different position than on DDR modules.

Higher-speed DDR2 DIMMs can be mixed with lower-speed DDR2 DIMMs, although the memory controller will operate all DIMMs at same speed as the lowest-speed DIMM present.

Relation to GDDR memory

The first commercial product to claim using the "DDR2" technology was the Nvidia GeForce FX 5800 graphics card. However, it is important to note that this GDDR2 memory used on graphics cards is not DDR2 per se, but rather an early midpoint between DDR and DDR2 technologies. Using "DDR2" to refer to GDDR2 is a colloquial misnomer. In particular, the performance-enhancing doubling of the I/O clock rate is missing. It had severe overheating issues due to the nominal DDR voltages. ATI has since designed the GDDR technology further into GDDR3, which is based on DDR2 SDRAM, though with several additions suited for graphics cards.

GDDR3 and GDDR5 is now commonly used in modern graphics cards and some tablet PCs. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use "GDDR2". These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards.

See also

Related Research Articles

DIMM computer memory module that have separate electrical contacts on each side of the module and a 64-bit data path

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Rambus DRAM (RDRAM), and its successors Concurrent Rambus DRAM (CRDRAM) and Direct Rambus DRAM (DRDRAM), are types of synchronous dynamic RAM developed by Rambus from the late-1980s through to the early-2000s. The third-generation of Rambus DRAM, DRDRAM was replaced by XDR DRAM. Rambus DRAM was developed for high-bandwidth applications, and was positioned by Rambus as replacement for various types of contemporary memories, such as SDRAM.


A SO-DIMM, SODIMM, or small outline dual in-line memory module, is a type of computer memory built using integrated circuits. SO-DIMMs are a smaller alternative to a DIMM, being roughly half the size of regular DIMMs.

PC100 is a standard for internal removable computer random access memory, defined by the JEDEC. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin DIMM and 144-pin SO-DIMM form factors. PC100 is backward compatible with PC66 and was superseded by the PC133 standard.

PC133 is a computer memory standard defined by the JEDEC. PC133 refers to SDR SDRAM operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168 pin DIMM and 144 pin SO-DIMM form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1066 MB per second. PC133 is backward compatible with PC100 and PC66.

Column Access Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM module, and the moment the data from the given array location is available on the module's output pins.

In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of parallel presence detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode much more information.

Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.

Fully Buffered DIMM

Fully Buffered DIMM is a memory technology that can be used to increase reliability and density of memory systems. Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module, i.e. via multidrop buses. As the memory width increases together with the access speed, the signal degrades at the interface between the bus and the device. This limits the speed and memory density, so FB-DIMMs take a different approach to solve the problem.

GDDR4 SGRAM, an abbreviation for double data rate type four synchronous graphics random access memory, is a type of graphics card memory specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM. GDDR4 is based on DDR3 SDRAM technology and was intended to replace the DDR2-based GDDR3, but it ended up being replaced by GDDR5 within a year.

GDDR5, an abbreviation for graphics double data rate type five synchronous random-access memory, is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth interface designed for use in graphics cards, game consoles, and high-performance computing.

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Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth interface.


Low-Power Double Data Rate Synchronous Dynamic Random Access Memory, commonly abbreviated as Low-Power DDR SDRAM or LPDDR SDRAM, is a type of double data rate synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers. It is also known as Mobile DDR, and abbreviated as mDDR.


Graphics DDR3 SDRAM is a type of DDR SDRAM specialized for graphics processing units (GPUs) offering less access latency and greater device bandwidths. Originally designed by ATI Technologies, it has since been adopted as a JEDEC standard.

High Bandwidth Memory high-performance RAM interface for 3D-stacked DRAM from AMD and Hynix

High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked DRAM from Samsung, AMD and Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices. The first devices to use HBM are the AMD Fiji GPUs.


  1. JEDEC JESD 208 (section 5, tables 15 and 16)
  2. "DDR2 SDRAM SPECIFICATION" (PDF). JESD79-2E. JEDEC. April 2008: 78. Retrieved 2009-03-14.
  3. "SPECIALITY DDR2-1066 SDRAM" (PDF). JEDEC. November 2007: 70. Retrieved 2009-03-14.
  4. Mushkin PC2-5300 vs. Corsair PC2-5400
  5. Ilya Gavrichenkov. "DDR2 vs. DDR: Revenge gained". X-bit Laboratories. Archived from the original on 2006-11-21.

Further reading

Note**: JEDEC website requires registration ($2,500 membership) for viewing or downloading of these documents: http://www.jedec.org/standards-documents