CAS latency

Last updated January 14, 2024

Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available.^[1]^[2] In asynchronous DRAM, the interval is specified in nanoseconds (absolute time).^[3] In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.

RAM operation background

Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal word line. Sending a logical high signal along a given row enables the MOSFETs present in that row, connecting each storage capacitor to its corresponding vertical bit line. Each bit line is connected to a sense amplifier that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh the row.

When no word line is active, the array is idle and the bit lines are held in a precharged^[4] state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.

To access memory, a row must first be selected and loaded into the sense amplifiers. This row is then active, and columns may be accessed for read or write.

The CAS latency is the delay between the time at which the column address and the column address strobe signal are presented to the memory module and the time at which the corresponding data is made available by the memory module. The desired row must already be active; if it is not, additional time is required.

As an example, a typical 1 GiB SDRAM memory module might contain eight separate one-gibibit DRAM chips, each offering 128 MiB of storage space. Each chip is divided internally into eight banks of 2²⁷=128 Mibits, each of which composes a separate DRAM array. Each bank contains 2¹⁴=16384 rows of 2¹³=8192 bits each. One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 13-bit column address.^{[ citation needed ]}

Effect on memory access speed

With asynchronous DRAM, memory was accessed by a memory controller on the memory bus based on a set timing rather than a clock, and was separate from the system bus.^[3] Synchronous DRAM, however, has a CAS latency that is dependent upon the clock rate. Accordingly, the CAS latency of an SDRAM memory module is specified in clock ticks instead of absolute time.^{[ citation needed ]}

Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, pipeline stalls can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.

Because modern DRAM modules' CAS latencies are specified in clock ticks instead of time, when comparing latencies at different clock speeds, latencies must be translated into absolute times to make a fair comparison; a higher numerical CAS latency may still be less time if the clock is faster. Likewise, a memory module which is underclocked could have its CAS latency cycle count reduced to preserve the same CAS latency time.^{[ citation needed ]}

Double data rate (DDR) RAM performs two transfers per clock cycle, and it is usually described by this transfer rate. Because the CAS latency is specified in clock cycles, and not transfers (which occur on both the rising and falling edges of the clock), it is important to ensure it is the clock rate (half of the transfer rate) which is being used to compute CAS latency times.^{[ citation needed ]}

Another complicating factor is the use of burst transfers. A modern microprocessor might have a cache line size of 64 bytes, requiring eight transfers from a 64-bit-wide (eight bytes) memory to fill. The CAS latency can only accurately measure the time to transfer the first word of memory; the time to transfer all eight words depends on the data transfer rate as well. Fortunately, the processor typically does not need to wait for all eight words; the burst is usually sent in critical word first order, and the first critical word can be used by the microprocessor immediately.

In the table below, data rates are given in million transfers—also known as megatransfers —per second (MT/s), while clock rates are given in MHz, million cycles per second.

Memory timing examples

Memory timing examples (CAS latency only)^{[ citation needed ]}^{[ original research? ]}
Generation	Type	Data rate	Transfer time^{[lower-alpha 1]}	Command rate^{[lower-alpha 2]}	Cycle time^{[lower-alpha 3]}	CAS latency	First word^{[lower-alpha 4]}	Fourth word^{[lower-alpha 4]}	Eighth word^{[lower-alpha 4]}
SDRAM	PC100	100 MT/s	10.000 ns	100 MHz	10.000 ns	2	20.00 ns	50.00 ns	90.00 ns
SDRAM	PC133	133 MT/s	7.500 ns	133 MHz	7.500 ns	3	22.50 ns	45.00 ns	75.00 ns
DDR SDRAM	DDR-333	333 MT/s	3.000 ns	166 MHz	6.000 ns	2.5	15.00 ns	24.00 ns	36.00 ns
	DDR-400	400 MT/s	2.500 ns	200 MHz	5.000 ns	3	15.00 ns	22.50 ns	32.50 ns
						2.5	12.50 ns	20.00 ns	30.00 ns
						2	10.00 ns	17.50 ns	27.50 ns
DDR2 SDRAM	DDR2-400	400 MT/s	2.500 ns	200 MHz	5.000 ns	4	20.00 ns	27.50 ns	37.50 ns
	DDR2-400	400 MT/s	2.500 ns	200 MHz	5.000 ns	3	15.00 ns	22.50 ns	32.50 ns
	DDR2-533	533 MT/s	1.875 ns	266 MHz	3.750 ns	4	15.00 ns	20.63 ns	28.13 ns
	DDR2-533	533 MT/s	1.875 ns	266 MHz	3.750 ns	3	11.25 ns	16.88 ns	24.38 ns
	DDR2-667	667 MT/s	1.500 ns	333 MHz	3.000 ns	5	15.00 ns	19.50 ns	25.50 ns
	DDR2-667	667 MT/s	1.500 ns	333 MHz	3.000 ns	4	12.00 ns	16.50 ns	22.50 ns
	DDR2-800	800 MT/s	1.250 ns	400 MHz	2.500 ns	6	15.00 ns	18.75 ns	23.75 ns
						5	12.50 ns	16.25 ns	21.25 ns
						4.5	11.25 ns	15.00 ns	20.00 ns
						4	10.00 ns	13.75 ns	18.75 ns
	DDR2-1066	1066 MT/s	0.938 ns	533 MHz	1.875 ns	7	13.13 ns	15.94 ns	19.69 ns
						6	11.25 ns	14.06 ns	17.81 ns
						5	9.38 ns	12.19 ns	15.94 ns
						4.5	8.44 ns	11.25 ns	15.00 ns
						4	7.50 ns	10.31 ns	14.06 ns
DDR3 SDRAM	DDR3-1066	1066 MT/s	0.938 ns	533 MHz	1.875 ns	7	13.13 ns	15.94 ns	19.69 ns
	DDR3-1333	1333 MT/s	0.750 ns	666 MHz	1.500 ns	9	13.50 ns	15.75 ns	18.75 ns
						7	10.50 ns	12.75 ns	15.75 ns
						6	9.00 ns	11.25 ns	14.25 ns
	DDR3-1375	1375 MT/s	0.727 ns	687 MHz	1.455 ns	5	7.27 ns	9.45 ns	12.36 ns
	DDR3-1600	1600 MT/s	0.625 ns	800 MHz	1.250 ns	11	13.75 ns	15.63 ns	18.13 ns
						10	12.50 ns	14.38 ns	16.88 ns
						9	11.25 ns	13.13 ns	15.63 ns
						8	10.00 ns	11.88 ns	14.38 ns
						7	8.75 ns	10.63 ns	13.13 ns
						6	7.50 ns	9.38 ns	11.88 ns
	DDR3-1866	1866 MT/s	0.536 ns	933 MHz	1.071 ns	10	10.71 ns	12.32 ns	14.46 ns
						9	9.64 ns	11.25 ns	13.39 ns
						8	8.57 ns	10.18 ns	12.32 ns
	DDR3-2000	2000 MT/s	0.500 ns	1000 MHz	1.000 ns	9	9.00 ns	10.50 ns	12.50 ns
	DDR3-2133	2133 MT/s	0.469 ns	1066 MHz	0.938 ns	12	11.25 ns	12.66 ns	14.53 ns
						11	10.31 ns	11.72 ns	13.59 ns
						10	9.38 ns	10.78 ns	12.66 ns
						9	8.44 ns	9.84 ns	11.72 ns
						8	7.50 ns	8.91 ns	10.78 ns
						7	6.56 ns	7.97 ns	9.84 ns
	DDR3-2200	2200 MT/s	0.455 ns	1100 MHz	0.909 ns	7	6.36 ns	7.73 ns	9.55 ns
	DDR3-2400	2400 MT/s	0.417 ns	1200 MHz	0.833 ns	13	10.83 ns	12.08 ns	13.75 ns
						12	10.00 ns	11.25 ns	12.92 ns
						11	9.17 ns	10.42 ns	12.08 ns
						10	8.33 ns	9.58 ns	11.25 ns
						9	7.50 ns	8.75 ns	10.42 ns
	DDR3-2600	2600 MT/s	0.385 ns	1300 MHz	0.769 ns	11	8.46 ns	9.62 ns	11.15 ns
	DDR3-2666	2666 MT/s	0.375 ns	1333 MHz	0.750 ns	15	11.25 ns	12.38 ns	13.88 ns
						13	9.75 ns	10.88 ns	12.38 ns
						12	9.00 ns	10.13 ns	11.63 ns
						11	8.25 ns	9.38 ns	10.88 ns
	DDR3-2800	2800 MT/s	0.357 ns	1400 MHz	0.714 ns	16	11.43 ns	12.50 ns	13.93 ns
						12	8.57 ns	9.64 ns	11.07 ns
						11	7.86 ns	8.93 ns	10.36 ns
	DDR3-2933	2933 MT/s	0.341 ns	1466 MHz	0.682 ns	12	8.18 ns	9.20 ns	10.57 ns
	DDR3-3000	3000 MT/s	0.333 ns	1500 MHz	0.667 ns	12	8.00 ns	9.00 ns	10.33 ns
	DDR3-3100	3100 MT/s	0.323 ns	1550 MHz	0.645 ns	12	7.74 ns	8.71 ns	10.00 ns
	DDR3-3200	3200 MT/s	0.313 ns	1600 MHz	0.625 ns	16	10.00 ns	10.94 ns	12.19 ns
	DDR3-3300	3300 MT/s	0.303 ns	1650 MHz	0.606 ns	16	9.70 ns	10.61 ns	11.82 ns
DDR4 SDRAM
	DDR4-1600	1600 MT/s	0.625 ns	800 MHz	1.250 ns	12	15.00 ns	16.88 ns	19.38 ns
						11	13.75 ns	15.63 ns	18.13 ns
						10	12.50 ns	14.38 ns	16.88 ns
	DDR4-1866	1866 MT/s	0.536 ns	933 MHz	1.071 ns	14	15.00 ns	16.61 ns	18.75 ns
						13	13.93 ns	15.54 ns	17.68 ns
						12	12.86 ns	14.46 ns	16.61 ns
	DDR4-2133	2133 MT/s	0.469 ns	1066 MHz	0.938 ns	16	15.00 ns	16.41 ns	18.28 ns
						15	14.06 ns	15.47 ns	17.34 ns
						14	13.13 ns	14.53 ns	16.41 ns
	DDR4-2400	2400 MT/s	0.417 ns	1200 MHz	0.833 ns	17	14.17 ns	15.42 ns	17.08 ns
						16	13.33 ns	14.58 ns	16.25 ns
						15	12.50 ns	13.75 ns	15.42 ns
	DDR4-2666	2666 MT/s	0.375 ns	1333 MHz	0.750 ns	19	14.25 ns	15.38 ns	16.88 ns
						17	12.75 ns	13.88 ns	15.38 ns
						16	12.00 ns	13.13 ns	14.63 ns
						15	11.25 ns	12.38 ns	13.88 ns
						13	9.75 ns	10.88 ns	12.38 ns
	DDR4-2800	2800 MT/s	0.357 ns	1400 MHz	0.714 ns	17	12.14 ns	13.21 ns	14.64 ns
						16	11.43 ns	12.50 ns	13.93 ns
						15	10.71 ns	11.79 ns	13.21 ns
						14	10.00 ns	11.07 ns	12.50 ns
	DDR4-3000	3000 MT/s	0.333 ns	1500 MHz	0.667 ns	17	11.33 ns	12.33 ns	13.67 ns
						16	10.67 ns	11.67 ns	13.00 ns
						15	10.00 ns	11.00 ns	12.33 ns
						14	9.33 ns	10.33 ns	11.67 ns
	DDR4-3200	3200 MT/s	0.313 ns	1600 MHz	0.625 ns	16	10.00 ns	10.94 ns	12.19 ns
						15	9.38 ns	10.31 ns	11.56 ns
						14	8.75 ns	9.69 ns	10.94 ns
	DDR4-3300	3300 MT/s	0.303 ns	1650 MHz	0.606 ns	16	9.70 ns	10.61 ns	11.82 ns
	DDR4-3333	3333 MT/s	0.300 ns	1666 MHz	0.600 ns	16	9.60 ns	10.50 ns	11.70 ns
	DDR4-3400	3400 MT/s	0.294 ns	1700 MHz	0.588 ns	16	9.41 ns	10.29 ns	11.47 ns
	DDR4-3466	3466 MT/s	0.288 ns	1733 MHz	0.577 ns	18	10.38 ns	11.25 ns	12.40 ns
						17	9.81 ns	10.67 ns	11.83 ns
						16	9.23 ns	10.10 ns	11.25 ns
	DDR4-3600	3600 MT/s	0.278 ns	1800 MHz	0.556 ns	19	10.56 ns	11.39 ns	12.50 ns
						18	10.00 ns	10.83 ns	11.94 ns
						17	9.44 ns	10.28 ns	11.39 ns
						16	8.89 ns	9.72 ns	10.83 ns
						15	8.33 ns	9.17 ns	10.28 ns
						14	7.78 ns	8.61 ns	9.72 ns
	DDR4-3733	3733 MT/s	0.268 ns	1866 MHz	0.536 ns	17	9.11 ns	9.91 ns	10.98 ns
	DDR4-3866	3866 MT/s	0.259 ns	1933 MHz	0.517 ns	18	9.31 ns	10.09 ns	11.12 ns
	DDR4-4000	4000 MT/s	0.250 ns	2000 MHz	0.500 ns	19	9.50 ns	10.25 ns	11.25 ns
						18	9.00 ns	9.75 ns	10.75 ns
						17	8.50 ns	9.25 ns	10.25 ns
						16	8.00 ns	8.75 ns	9.75 ns
	DDR4-4133	4133 MT/s	0.242 ns	2066 MHz	0.484 ns	19	9.19 ns	9.92 ns	10.89 ns
	DDR4-4200	4200 MT/s	0.238 ns	2100 MHz	0.476 ns	19	9.05 ns	9.76 ns	10.71 ns
	DDR4-4266	4266 MT/s	0.234 ns	2133 MHz	0.469 ns	19	8.91 ns	9.61 ns	10.55 ns
						18	8.44 ns	9.14 ns	10.08 ns
						17	7.97 ns	8.67 ns	9.61 ns
						16	7.50 ns	8.20 ns	9.14 ns
	DDR4-4400	4400 MT/s	0.227 ns	2200 MHz	0.454 ns	19	8.64 ns	9.32 ns	10.23 ns
						18	8.18 ns	8.86 ns	9.77 ns
						17	7.73 ns	8.41 ns	9.32 ns
	DDR4-4600	4600 MT/s	0.217 ns	2300 MHz	0.435 ns	19	8.26 ns	8.91 ns	9.78 ns
	DDR4-4600	4600 MT/s	0.217 ns	2300 MHz	0.435 ns	18	7.82 ns	8.48 ns	9.35 ns
	DDR4-4800	4800 MT/s	0.208 ns	2400 MHz	0.417 ns	20	8.33 ns	8.96 ns	9.79 ns
	DDR4-4800	4800 MT/s	0.208 ns	2400 MHz	0.417 ns	19	7.92 ns	8.54 ns	9.38 ns
DDR5 SDRAM
	DDR5-4800	4800 MT/s	0.208 ns	2400 MHz	0.417 ns	40	16.67 ns	17.29 ns	18.13 ns
						38	15.83 ns	16.46 ns	17.29 ns
						36	15.00 ns	15.63 ns	16.46 ns
						34	14.17 ns	14.79 ns	15.63 ns
	DDR5-5200	5200 MT/s	0.192 ns	2600 MHz	0.385 ns	40	15.38 ns	15.96 ns	16.73 ns
						38	14.62 ns	15.19 ns	15.96 ns
						36	13.85 ns	14.42 ns	15.19 ns
						34	13.08 ns	13.65 ns	14.42 ns
	DDR5-5600	5600 MT/s	0.179 ns	2800 MHz	0.357 ns	40	14.29 ns	14.82 ns	15.54 ns
						38	13.57 ns	14.11 ns	14.82 ns
						36	12.86 ns	13.39 ns	14.11 ns
						34	12.14 ns	12.68 ns	13.39 ns
						30	10.71 ns	11.25 ns	11.96 ns
	DDR5-6000	6000 MT/s	0.167 ns	3000 MHz	0.333 ns	40	13.33 ns	13.83 ns	14.50 ns
						38	12.67 ns	13.17 ns	13.83 ns
						36	12.00 ns	12.50 ns	13.17 ns
						32	10.67 ns	11.17 ns	11.83 ns
						30	10.00 ns	10.50 ns	11.17 ns
	DDR5-6200	6200 MT/s	0.161 ns	3100 MHz	0.323 ns	40	12.90 ns	13.39 ns	14.03 ns
						38	12.26 ns	12.74 ns	13.39 ns
						36	11.61 ns	12.10 ns	12.74 ns
	DDR5-6400	6400 MT/s	0.156 ns	3200 MHz	0.313 ns	40	12.50 ns	12.97 ns	13.59 ns
						38	11.88 ns	12.34 ns	12.97 ns
						36	11.25 ns	11.72 ns	12.34 ns
						34	10.63 ns	11.09 ns	11.72 ns
						32	10.00 ns	10.47 ns	11.09 ns
	DDR5-6600	6600 MT/s	0.152 ns	3300 MHz	0.303 ns	34	10.30 ns	10.76 ns	11.36 ns
Generation	Type	Data rate	Transfer time	Command rate	Cycle time	CAS latency	First word	Fourth word	Eighth word

Notes

↑ Transfer time = 1 / Data rate.
↑ Command rate = Data rate / 2 for double data rate (DDR), Command rate = Data rate for single data rate (SDR).
↑ Cycle time = 1 / Command rate = 2 × Transfer time.
1 2 3 Nth word = [(2 × CAS latency) + (N − 1)] × Transfer time.

Related Research Articles

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References

↑ Stokes, Jon "Hannibal" (1998–2004). "Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM". Ars Technica. Archived from the original on 2012-11-01.
↑ Jacob, Bruce L. (December 10, 2002), Synchronous DRAM Architectures, Organizations, and Alternative Technologies (PDF), University of Maryland
1 2 Memory technology evolution: an overview of system memory technologies, HP, July 2008
↑ Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (December 4, 2007). DRAM Circuit Design: Fundamental and High-Speed Topics. John Wiley & Sons. ISBN 978-0470184752.

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[5] Transfer time = 1 / Data rate.

[6] Command rate = Data rate / 2 for double data rate (DDR), Command rate = Data rate for single data rate (SDR).

[7] Cycle time = 1 / Command rate = 2 × Transfer time.

[nthword-8] 1 2 3 Nth word = [(2 × CAS latency) + (N − 1)] × Transfer time.

[1] Stokes, Jon "Hannibal" (1998–2004). "Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM". Ars Technica. Archived from the original on 2012-11-01.

[umd-2] Jacob, Bruce L. (December 10, 2002), Synchronous DRAM Architectures, Organizations, and Alternative Technologies (PDF), University of Maryland

[async-3] 1 2 Memory technology evolution: an overview of system memory technologies, HP, July 2008

[4] Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (December 4, 2007). DRAM Circuit Design: Fundamental and High-Speed Topics. John Wiley & Sons. ISBN 978-0470184752.

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