|Computer memory types|
|Early stage NVRAM|
Synchronous dynamic random-access memory (SDRAM) is any dynamic random-access memory (DRAM) where the operation of its external pin interface is coordinated by an externally supplied clock signal.
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
DRAM integrated circuits (ICs) produced from the early 1970s to early 1990s used an asynchronous interface, in which input control signals have a direct effect on internal functions only delayed by the trip across its semiconductor pathways. SDRAM has a synchronous interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called banks , allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an interleaved fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.
An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny MOS transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body.
A memory bank is a logical unit of storage in electronics, which is hardware-dependent. In a computer, the memory bank may be determined by the memory controller along with physical organization of the hardware memory slots. In a typical synchronous dynamic random-access memory (SDRAM) or double data rate synchronous dynamic random-access memory, a bank consists of multiple rows and columns of storage units, and is usually spread out across several chips. In a single read or write operation, only one bank is accessed, therefore the number of bits in a column or a row, per bank and per chip, equals the memory bus width in bits. The size of a bank is further determined by the number of bits in a column and a row, per chip, multiplied by the number of chips in a bank.
Pipelining means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.
In computing, a pipeline, also known as a data pipeline, is a set of data processing elements connected in series, where the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion. Some amount of buffer storage is often inserted between elements.
The first commercial SDRAM was the Samsung KM48SL2000 chip, introduced in 1992. SDRAM is widely used in computers. Beyond the original SDRAM, further generations of double data rate RAM have entered the mass market – DDR (also known as DDR1), DDR2, DDR3, and DDR4, with the latest generation (DDR4) released in the second half of 2014.
Samsung Electronics Co., Ltd. is a South Korean multinational electronics company headquartered in Suwon, South Korea. Due to some circular ownership, it is the flagship company of the Samsung chaebol, accounting for 70% of the group's revenue in 2012. Samsung Electronics has assembly plants and sales networks in 80 countries and employs around 308,745 people. It is the world's largest manufacturer of consumer electronics and semiconductors by revenue. As of June 2018, Samsung Electronics' market cap stood at US$325.9 billion.
A computer is a machine that can be instructed to carry out sequences of arithmetic or logical operations automatically via computer programming. Modern computers have the ability to follow generalized sets of operations, called programs. These programs enable computers to perform an extremely wide range of tasks. A "complete" computer including the hardware, the operating system, and peripheral equipment required and used for "full" operation can be referred to as a computer system. This term may as well be used for a group of computers that are connected and work together, in particular a computer network or computer cluster.
In computing, a computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used in the context of NAND flash memory.
The first commercial synchronous DRAM was the Samsung KM48SL2000 chip, which had a capacity of 16 Mb. It was introduced by Samsung Electronics in 1992, and mass-produced in 1993. By 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater performance.
The mebibit is a multiple of the bit, a unit of information, prefixed by the standards-based multiplier "mebi" (symbol Mi), a binary prefix meaning 220. The unit symbol of the mebibit is Mibit.
SDRAM latency is not inherently lower (faster) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth.
In computing, bandwidth is the maximum rate of data transfer across a given path. Bandwidth may be characterized as network bandwidth, data bandwidth, or digital bandwidth.
Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM.
Double data rate SDRAM, known as DDR SDRAM, was first demonstrated by Samsung in 1997. Mb) in June 1998, followed soon after by Hyundai Electronics (now SK Hynix) the same year.Samsung released the first commercial DDR SDRAM chip (64
SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations.
Today, the world's largest manufacturers of SDRAM include: Samsung Electronics, Panasonic, Micron Technology, and Hynix.
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.
Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).
Originally simply known as SDRAM, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMMs that read or write 64 (non-ECC) or 72 (ECC) bits at a time.
Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.
Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V.
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly active low, which are sampled on the rising edge of the clock:
SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
The commands are defined as follows:
|H||x||x||x||x||x||x||Command inhibit (no operation)|
|L||H||H||L||x||x||x||Burst terminate: stop a burst read or burst write in progress|
|L||H||L||H||bank||L||column||Read: read a burst of data from the currently active row|
|L||H||L||H||bank||H||column||Read with auto precharge: as above, and precharge (close row) when done|
|L||H||L||L||bank||L||column||Write: write a burst of data to the currently active row|
|L||H||L||L||bank||H||column||Write with auto precharge: as above, and precharge (close row) when done|
|L||L||H||H||bank||row||Active (activate): open a row for read and write commands|
|L||L||H||L||bank||L||x||Precharge: deactivate (close) the current row of selected bank|
|L||L||H||L||x||H||x||Precharge all: deactivate (close) the current row of all banks|
|L||L||L||H||x||x||x||Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.|
|L||L||L||L||0 0||mode||Load mode register: A0 through A9 are loaded to configure the DRAM chip.|
The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:
For example, a 512 MB SDRAM DIMM (which contains 512 MiB (mebibytes) = 512 × 220 bytes = 536,870,912 bytes exactly), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM chip internally contains four independent 16 MB (MiB) memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (1024 16-bit columns). A bank is either idle, active, or changing from one to the other.
The active command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refreshing the dynamic (capacitive) memory storage cells of that row.
Once the row has been activated or "opened", read and write commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or tRCD before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an active command, and a read or write command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.
Both read and write commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).
When a read command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.
A write command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.
When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, tRP, which must elapse before that bank is fully idle and it may receive another activate command.
Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time tRAS delay between an active command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.
The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time tRFC to return the chip to the idle state. (This time is usually equal to tRCD+tRP.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, tRCD before the row is fully open and can accept read and write commands.
When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.
A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.
If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.
Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.
Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect).
Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required.
If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.
A modern microprocessor with a cache will generally access memory in units of cache lines. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word bursts. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.
Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.
For the sequential burst mode, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an exclusive or operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2. [ citation needed ]Although more confusing to humans, this can be easier to implement in hardware, and is preferred by Intel for its microprocessors.
If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.
Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode register write.
The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.
Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).
It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 4096 in the example we have been using) every refresh interval (tREF = 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued.
As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is permissible to change the clock rate, or even stop the clock entirely.
If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.
If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval tREF, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.
Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.
SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in Mobile DDR (LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE.
DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple data words located on a common physical row in the memory.
The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases: bitline precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as the sense amplifiers also act as latches. For reference, a row of a 1 Gbit DDR3 device is 2,048 bits wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50 ns, depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns.
Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.
The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result in multiple data words.
In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock
The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as DDR3), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s), or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth.
Each generation of SDRAM has a different prefetch buffer size:
|DDR2||Access is ≥4 words|
"Burst terminate" removed
4 units used in parallel
1.25 - 5 ns per cycle
Internal operations are at 1/2 the clock rate.
Signal: SSTL_18 (1.8V)
|DDR3||Access is ≥8 words|
Signal: SSTL_15 (1.5V)
Much longer CAS latencies
|DDR4||Vcc ≤ 1.2 V point-to-point (single module per channel)|
This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors EDO-RAM and FPM-RAM which took typically two or three clocks to transfer one word of data.
While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a double data rate interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.
DDR SDRAM (sometimes called DDR1 for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.
Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.
DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.
Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.
Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).
DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a 400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second.
Again, with every doubling, the downside is the increased latency. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a CAS latency of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).
DDR3 memory chips are being made commercially, MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2800 (PC3 22400 modules) are available.and computer systems using them were available from the second half of 2007, with significant usage from 2008 onwards. Initial clock rates were 400 and 533
DDR4 SDRAM is the successor to DDR3 SDRAM. It was revealed at the Intel Developer Forum in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012,and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 is expected to reach mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.
The new chips are expected to run at 1.2 V or less, compared to the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.
DDR4 will not double the internal prefetch width again, but will use the same 8n prefetch as DDR3.Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.
In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung announced the completion and release for testing of a 30 nm 2 GB DDR4 DRAM module. It has a maximum bandwidth of 2.13 Gbit/s at 1.2 V, uses pseudo open drain technology and draws 40% less power than an equivalent DDR3 module.
In March 2017, JEDEC announced a DDR5 standard is under development,but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018.
In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM.
RDRAM was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR DRAM.
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.). SLDRAM was an open standard and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like DDR SDRAM, SLDRAM uses a double-pumped bus, giving it an effective speed of 400, 600, or 800 MT/s.
SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.
The basic read/write command consisted of (beginning with CA9 of the first word):
Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)
A read/write command had the msbit clear:
A notable omission from the specification was per-byte write enables; it was designed for systems with caches and ECC memory, which always write in multiples of a cache line.
Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.
There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.
VCM was a proprietary type of SDRAM that was designed by NEC, but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of RDRAM because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the memory controller. In the late 1990s, a number of PC northbridge chipsets (such as the popular VIA KX133 and KT133) included VCSDRAM support.
VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)
To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.
Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a 17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.
Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM cells. The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.
The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.
A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits (256 bytes) in a segment.
Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as texture memory and framebuffers, found on video cards. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.
The earliest known SGRAM memory are 8 Mb chips dating back to 1994: the Hitachi HM5283206, introduced in November 1994, and the NEC µPD481850, introduced in December 1994. The earliest known commercial device to use SGRAM is Sony's PlayStation (PS) video game console, starting with the Japanese SCPH-5000 model released in December 1995, using the NEC µPD481850 chip.
Graphics double data rate SDRAM (GDDR SDRAM) is a type of specialized DDR SDRAM designed to be used as the main memory of graphics processing units (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2018, there are six, successive generations of GDDR: GDDR2, GDDR3, GDDR4, GDDR5, and GDDR5X, GDDR6.
GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16 Mb memory chip by Samsung Electronics in 1998.
High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked SDRAM from Samsung, AMD and SK Hynix. It is designed to be used in conjunction with high-performance graphics accelerators and network devices.The first HBM memory chip was produced by SK Hynix in 2013.
|Date of introduction||Chip name||Capacity (bits)||SDRAM type||Manufacturer(s)||Process||MOSFET||Area||Ref|
|1996||MSM5718C50||18 Mb||RDRAM||Oki||?||CMOS||325 mm²|
|1996||N64 RDRAM||36 Mb||RDRAM||NEC||?||CMOS||?|
|1996||?||1 Gb||SDR||Mitsubishi||150 nm||CMOS||?|
|1998||MD5764802||64 Mb||RDRAM||Oki||?||CMOS||325 mm²|
|March 1998||Direct RDRAM||72 Mb||RDRAM||Rambus||?||CMOS||?|
|June 1998||?||64 Mb||DDR||Samsung||?||CMOS||?|
|1999||?||1 Gb||DDR||Samsung||140 nm||CMOS||?|
|2000||GS eDRAM||32 Mb||eDRAM||Sony, Toshiba||180 nm||CMOS||279 mm²|
|2003||EE+GS eDRAM||32 Mb||eDRAM||Sony, Toshiba||90 nm||CMOS||86 mm²|
|2003||?||72 Mb||DDR3||Samsung||90 nm||CMOS||?|
|2003||?||512 Mb||DDR2||Elpida||110 nm||CMOS||?|
|2004||?||2 Gb||DDR2||Samsung||80 nm||CMOS||?|
|2005||EE+GS eDRAM||32 Mb||eDRAM||Sony, Toshiba||65 nm||CMOS||86 mm²|
|2005||Xenos eDRAM||80 Mb||eDRAM||NEC||90 nm||CMOS||?|
|2005||?||512 Mb||DDR3||Samsung||80 nm||CMOS||?|
|2006||?||1 Gb||DDR2||Hynix||60 nm||CMOS||?|
|April 2008||?||8 Gb||DDR3||Samsung||50 nm||CMOS||?|
|2008||?||16 Gb||DDR3||Samsung||50 nm||CMOS||?|
|2009||?||2 Gb||DDR3||Hynix||40 nm||CMOS||?|
|2011||?||16 Gb||DDR3||Hynix||40 nm||CMOS||?|
|2011||?||2 Gb||DDR4||Hynix||30 nm||CMOS||?|
|2014||?||8 Gb||LPDDR4||Samsung||20 nm||CMOS||?|
|2015||?||12 Gb||LPDDR4||Samsung||20 nm||CMOS||?|
|2018||?||8 Gb||LPDDR5||Samsung||10 nm||FinFET||?|
|2018||?||128 Gb||DDR4||Samsung||10 nm||FinFET||?|
|Date of introduction||Chip name||Capacity (bits)||SDRAM type||Manufacturer(s)||Process||MOSFET||Area||Ref|
|November 1994||HM5283206||8 Mb||SGRAM (SDR)||Hitachi||350 nm||CMOS||58 mm²|
|December 1994||µPD481850||8 Mb||SGRAM (SDR)||NEC||?||CMOS||280 mm²|
|1997||µPD4811650||16 Mb||SGRAM (SDR)||NEC||350 nm||CMOS||280 mm²|
|September 1998||?||16 Mb||SGRAM (GDDR)||Samsung||?||CMOS||?|
|1999||KM4132G112||32 Mb||SGRAM (SDR)||Samsung||?||CMOS||?|
|2002||?||128 Mb||SGRAM (GDDR2)||Samsung||?||CMOS||?|
|2003||?||256 Mb||SGRAM (GDDR2)||Samsung||?||CMOS||?|
|2003||?||256 Mb||SGRAM (GDDR3)||Samsung||?||CMOS||?|
|March 2005||K4D553238F||256 Mb||SGRAM (GDDR)||Samsung||?||CMOS||77 mm²|
|October 2005||?||256 Mb||SGRAM (GDDR4)||Samsung||?||CMOS||?|
|2005||?||512 Mb||SGRAM (GDDR4)||Hynix||?||CMOS||?|
|2007||?||1 Gb||SGRAM (GDDR5)||Hynix||60 nm||CMOS||?|
|2009||?||2 Gb||SGRAM (GDDR5)||Hynix||40 nm||CMOS||?|
|2010||K4W1G1646G||1 Gb||SGRAM (GDDR3)||Samsung||?||CMOS||100 mm²|
|2012||?||4 Gb||SGRAM (GDDR3)||SK Hynix||?||CMOS||?|
|March 2016||MT58K256M32JA||8 Gb||SGRAM (GDDR5X)||Micron||20 nm||CMOS||140 mm²|
|June 2016||?||32 Gb||HBM2||Samsung||20 nm||CMOS||?|
|2017||?||64 Gb||HBM2||Samsung||20 nm||CMOS||?|
|January 2018||K4ZAF325BM||16 Gb||SGRAM (GDDR6)||Samsung||10 nm||FinFET||?|
Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, and DDR4 memory modules will not work in DDR1-equipped motherboards, and vice versa.
Static random-access memory is a type of semiconductor random-access memory (RAM) that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
A DIMM or dual in-line memory module comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs as the predominant type of memory module as Intel P5-based Pentium processors began to gain market share.
Double Data Rate 2 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR2 SDRAM, is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by DDR3 SDRAM. DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.
Semiconductor memory is a digital electronic data storage device, implemented with semiconductor devices. It is often used as computer memory, implemented with metal-oxide-semiconductor (MOS) memory cells on an integrated circuit (IC) chip. There are many different types of implementations using various technologies.
Column Access Strobe (CAS) latency, or CL, is the delay time between the READ command and the moment data is available. In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.
XDR DRAM or extreme data rate dynamic random-access memory is a high-performance RAM interface and successor to the Rambus RDRAM it is based on, competing with the rival DDR2 SDRAM and GDDR4 technology.
Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
XDR2 DRAM was a proposed type of dynamic random-access memory that was offered by Rambus. It was announced on July 7, 2005 and the specification for which was released on March 26, 2008. Rambus has designed XDR2 as an evolution of, and the successor to, XDR DRAM.
Memory refresh is the process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information. Memory refresh is a background maintenance process required during the operation of semiconductor dynamic random-access memory (DRAM), the most widely used type of computer memory, and in fact is the defining characteristic of this class of memory.
Fully Buffered DIMM is a memory technology that can be used to increase reliability and density of memory systems. Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module, i.e. via multidrop buses. As the memory width increases together with the access speed, the signal degrades at the interface between the bus and the device. This limits the speed and memory density, so FB-DIMMs take a different approach to solve the problem.
GDDR4 SGRAM, an abbreviation for double data rate type four synchronous graphics random access memory, is a type of graphics card memory specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM. GDDR4 is based on DDR3 SDRAM technology and was intended to replace the DDR2-based GDDR3, but it ended up being replaced by GDDR5 within a year.
GDDR5, an abbreviation for graphics double data rate type five synchronous dynamic random-access memory, is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth interface designed for use in graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM.
Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth interface.
Random-access memory is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
Low-Power Double Data Rate Synchronous Dynamic Random Access Memory, commonly abbreviated as Low-Power DDR SDRAM or LPDDR SDRAM, is a type of double data rate synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers. It is also known as Mobile DDR, and abbreviated as mDDR.
Graphics DDR3 SDRAM is a type of DDR SDRAM specialized for graphics processing units (GPUs) offering less access latency and greater device bandwidths. Its specification was developed by ATI Technologies in collaboration with DRAM vendors including Elpida Memory, Hynix Semiconductor, Infineon and Micron. It was later adopted as a JEDEC standard.
High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked SDRAM from Samsung, AMD and SK Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015.
The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.