Memistor

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Memistor

A memistor is a nanoelectric circuitry element used in parallel computing memory technology. Essentially, a resistor with memory able to perform logic operations and store information, it is a three-terminal implementation of the memristor.

Contents

History

While the memristor is defined in terms of a two-terminal circuit element, there was an implementation of a three-terminal device called a memistor developed by Bernard Widrow in 1960. Memistors formed basic components of a neural network architecture called ADALINE developed by Widrow. [1] [2] The memistor was also used in MADALINE.

Essence

In one of the technical reports [3] the memistor was described as follows:

Like the transistor, the memistor is a 3-terminal element. The conductance between two of the terminals is controlled by the time integral of the current in the third, rather than its instantaneous value as in the transistor. Reproducible elements have been made which are continuously variable (thousands of possible analog storage levels), and which typically vary in resistance from 100 ohms to 1 ohm, and cover this range in about 10 seconds with several milliamperes of plating current. Adaptation is accomplished by direct current while sensing the neuron logical structure is accomplished nondestructively by passing alternating currents through the arrays of memistor cells.

Since the conductance was described as being controlled by the time integral of current as in Chua's theory of the memristor, the memistor of Widrow may be considered as a form of memristor having three instead of two terminals. However, one of the main limitations of Widrow's memistors was that they were made from an electroplating cell rather than as a solid-state circuit element. Solid-state circuit elements were required to achieve the scalability of the integrated circuit which was gaining popularity around the same time as the invention of Widrow's memistor.

An article on ArXiv suggests that the floating-gate MOSFET as well as other 3-terminal "memory transistors" may be modeled using dynamical systems equations in a similar fashion to the memristive systems of memristors. [4]

See also

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Trancitor

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Electrochemical Random-Access Memory (ECRAM) is a type of non-volatile memory (NVM) with multiple levels per cell (MLC) designed for deep learning analog acceleration. An ECRAM cell is a three-terminal device composed of a conductive channel, an insulating electrolyte, an ionic reservoir, and metal contacts. The resistance of the channel is modulated by ionic exchange at the interface between the channel and the electrolyte upon application of an electric field. The charge-transfer process allows both for state retention in the absence of applied power, and for programming of multiple distinct levels, both differentiating ECRAM operation from the one of a field-effect transistor (FET). The write operation is deterministic and can result in symmetrical potentiation and depression, making ECRAM arrays attractive for acting as artificial synaptic weights in physical implementations of artificial neural networks (ANN). The technology challenges include open circuit potential (OCP) and semiconductor foundry compatibility associated with energy materials. Universities, government laboratories, and corporate research teams have contributed to the development of ECRAM for analog computing. Notably, Sandia National Laboratories designed a lithium-based cell inspired by solid-state battery materials, Stanford University built an organic proton-based cell, and International Business Machines (IBM) demonstrated in-memory selector-free parallel programming for a logistic regression task in an array of metal-oxide ECRAM designed for insertion in the back end of line (BEOL).

References

  1. Youtube: widrowlms: Science in Action
  2. 1960: An adaptive "ADALINE" neuron using chemical "memistors"
  3. Widrow, B.; Pierce, W. H.; Angell, J.B. (1961), "Birth, Life, and Death in Microelectronic Systems" (PDF), Technical Report No. 1552-2/1851-1
  4. Mouttet, Blaise (2010). "Memristive Systems Analysis of 3-Terminal Devices". arXiv: 1012.5124 [cond-mat.mes-hall].