Memory cell (computing)

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Layout for the silicon implementation of a six transistor SRAM memory cell. 6T SRAM memory cell layout.jpg
Layout for the silicon implementation of a six transistor SRAM memory cell.

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.


Over the history of computing, different memory cell architectures have been used, including core memory and bubble memory. Today, the most common memory cell architecture is MOS memory, which consists of metal–oxide–semiconductor (MOS) memory cells. Modern random-access memory (RAM) uses MOS field-effect transistors (MOSFETs) as flip-flops, along with MOS capacitors for certain types of RAM.

The SRAM (static RAM) memory cell is a type of flip-flop circuit, typically implemented using MOSFETs. These require very low power to keep the stored value when not being accessed. A second type, DRAM (dynamic RAM), is based around MOS capacitors. Charging and discharging a capacitor can store a '1' or a '0' in the cell. However, the charge in this capacitor will slowly leak away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but can achieve greater storage densities.

On the other hand, most non-volatile memory (NVM) are based on floating-gate memory cell architecture. Non-volatile memory technologies including EPROM, EEPROM and flash memory use floating-gate memory cells, which are based around floating-gate MOSFET transistors.


The memory cell is the fundamental building block of memory. It can be implemented using different technologies, such as bipolar, MOS, and other semiconductor devices. It can also be built from magnetic material such as ferrite cores or magnetic bubbles. [1] Regardless of the implementation technology used, the purpose of the binary memory cell is always the same. It stores one bit of binary information that can be accessed by reading the cell and it must be set to store a 1 and reset to store a 0. [2]


Square array of DRAM memory cells being read Square array of mosfet cells read.png
Square array of DRAM memory cells being read

Logic circuits without memory cells or feedback paths are called combinational, their outputs values depend only on the current value of their input values. They do not have memory. But memory is a key element of digital systems. In computers, it allows to store both programs and data and memory cells are also used for temporary storage of the output of combinational circuits to be used later by digital systems. Logic circuits that use memory cells are called sequential circuits. Its output depends not only on the present value of its inputs, but also on the circuits previous state, as determined by the values stored on its memory cells. These circuits require a timing generator or clock for their operation. [3]

Computer memory used in most contemporary computer systems is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (Static RAM) cells, which has its value always available. That is the reason why SRAM memory is used for on-chip cache included in modern microprocessor chips. [4]


32x32 core memory plane storing 1024 bits of data. KL CoreMemory.jpg
32x32 core memory plane storing 1024  bits of data.

On December 11, 1946 Freddie Williams applied for a patent on his cathode-ray tube (CRT) storing device (Williams tube) with 128 40-bit words. It was operational in 1947 and is considered the first practical implementation of random-access memory (RAM). [5] In that year, the first patent applications for magnetic-core memory were filed by Frederick Viehe. [6] [7] Practical magnetic-core memory was developed by An Wang in 1948, and improved by Jay Forrester and Jan A. Rajchman in the early 1950s, before being commercialised with the Whirlwind computer in 1953. [8] Ken Olsen also contributed to its development. [9]

Semiconductor memory began in the early 1960s with bipolar memory cells, made of bipolar transistors. While it improved performance, it could not compete with the lower price of magnetic-core memory. [10]

MOS memory cells

Intel 1103, a 1970 metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) chip. Intel C1103.jpg
Intel 1103, a 1970 metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) chip.

The invention of the MOSFET (metal-oxide-semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959, [11] enabled the practical use of metal–oxide–semiconductor (MOS) transistors as memory cell storage elements, a function previously served by magnetic cores. [12] The first modern memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS (PMOS) static random-access memory (SRAM). [13] [14]

SRAM typically has six-transistor cells, whereas DRAM (dynamic random-access memory) typically has single-transistor cells. [15] [13] In 1965, Toshiba's Toscal BC-1411 electronic calculator used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors. [16] [17] MOS technology is the basis for modern DRAM. In 1966, Dr. Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell. [18] In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology. [19]

The first commercial bipolar 64-bit SRAM was released by Intel in 1969 with the 3101 Schottky TTL. One year later, it released the first DRAM integrated circuit chip, the Intel 1103, based on MOS technology. By 1972, it beat previous records in semiconductor memory sales. [20] DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s. [15] [13]

CMOS memory was commercialized by RCA, which launched a 288-bit CMOS SRAM memory chip in 1968. [21] CMOS memory was initially slower than NMOS memory, which was more widely used by computers in the 1970s. [22] In 1978, Hitachi introduced the twin-well CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a 3 µm process. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computer memory in the 1980s. [22]

The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells. [23] Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure. [24] Both debuted in 1984, when Hitachi introduced trench-capacitor memory and Fujitsu introduced stacked-capacitor memory. [23]

Floating-gate MOS memory cells

The floating-gate MOSFET (FGMOS) was invented by Dawon Kahng and Simon Sze at Bell Labs in 1967. [25] They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to produce reprogrammable ROM (read-only memory). [26] Floating-gate memory cells later became the basis for non-volatile memory (NVM) technologies including EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM) and flash memory. [27]

Flash memory was invented by Fujio Masuoka at Toshiba in 1980. [28] [29] Masuoka and his colleagues presented the invention of NOR flash in 1984, [30] and then NAND flash in 1987. [31] Multi-level cell (MLC) flash memory was introduced by NEC, which demonstrated quad-level cells in a 64  Mb flash chip storing 2-bit per cell in 1996. [23] 3D V-NAND, where flash memory cells are stacked vertically using 3D charge trap flash (CTP) technology, was first announced by Toshiba in 2007, [32] and first commercially manufactured by Samsung Electronics in 2013. [33] [34]


The following schematics detail the three most used implementations for memory cells :

DRAM Cell (1 Transistor and one capacitor) DRAM Cell Structure (Model of Single Circuit Cell).PNG
DRAM Cell (1 Transistor and one capacitor)
SRAM Cell (6 Transistors) SRAM Cell (6 Transistors).svg
SRAM Cell (6 Transistors)
Clocked J/K flip flop FlipflopJKlogic.png
Clocked J/K flip flop


DRAM memory cell

Die of the MT4C1024 integrating one-mebibit of DRAM memory cells. MT4C1024-HD.jpg
Die of the MT4C1024 integrating one-mebibit of DRAM memory cells.


The storage element of the DRAM memory cell is the capacitor labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. The nMOS transistor (3) acts as a gate to allow reading or writing when open or storing when closed. [35]


For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the nMOS transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a parasitic capacitance (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read. [36]


The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates the nMOS transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3). [36]

SRAM memory cell

SRAM memory cell depicting Inverter Loop as gates SRAM Cell Inverter Loop.png
SRAM memory cell depicting Inverter Loop as gates
An animated SR latch. Black and white mean logical '1' and '0', respectively.
(A) S = 1, R = 0: set
(B) S = 0, R = 0: hold
(C) S = 0, R = 1: reset
(D) S = 1, R = 1: not allowed
Transitioning from the restricted combination (D) to (A) leads to an unstable state. SRLatch-lowres.gif
An animated SR latch. Black and white mean logical '1' and '0', respectively.
(A) S = 1, R = 0: set
(B) S = 0, R = 0: hold
(C) S = 0, R = 1: reset
(D) S = 1, R = 1: not allowed
Transitioning from the restricted combination (D) to (A) leads to an unstable state.


The working principle of SRAM memory cell can be easier to understand if the transistors M1 through M4 are drawn as logic gates. That way it is clear that at its heart, the cell storage is built by using two cross-coupled inverters. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After been inverted twice it will also feedback the same value. [37]
Therefore there are only two stable states that the circuit can be in:
  • = 0 and   = 1
  • = 1 and   = 0


To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line (), they become conductive and so the and   values get transmitted to the bit line () and to its complement (). [37] Finally this values get amplified at the end of the bit lines. [37]


The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line () and the inverted one into its complement (). Next transistors M5 and M6 are open by driving a logic one (voltage high) into the word line (). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:
  1. If the value of the loop is the same as the new value driven, there is no change.
  2. If the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail. [37]

Flip flop

The flip-flop has many different implementations, its storage element is usually a Latch consisting of a NAND gate loop or a NOR gate loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using MOSFET transistors.

Floating gate

A flash memory cell Flash cell structure.svg
A flash memory cell

Floating-gate memory cells, based on floating-gate MOSFET transistors, are used for most non-volatile memory (NVM) technologies, including EPROM, EEPROM and flash memory. [27] According to R. Bez and A. Pirovano:

A floating-gate memory cell is basically an MOS transistor with a gate completely surrounded by dielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor. [27]

See also

Related Research Articles

Computer memory physical device used to store information for immediate use in a digital electronic device

In computing, memory refers to a device that is used to store information for immediate use in a computer or related computer hardware device. It typically refers to semiconductor memory, specifically metal–oxide–semiconductor (MOS) memory, where data is stored within MOS memory cells on a silicon integrated circuit chip. The term "memory" is often synonymous with the term "primary storage". Computer memory operates at a high speed, for example random-access memory (RAM), as a distinction from storage that provides slow-to-access information but offers higher capacities. If needed, contents of the computer memory can be transferred to secondary storage; a very common way of doing this is through a memory management technique called "virtual memory". An archaic synonym for memory is store.

MOSFET Transistor used for amplifying or switching electronic signals.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a type of insulated-gate field-effect transistor (IGFET) that is fabricated by the controlled oxidation of a semiconductor, typically silicon. The voltage of the covered gate determines the electrical conductivity of the device; this ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The MOSFET was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in November 1959. It is the basic building block of modern electronics, and the most frequently manufactured device in history, with an estimated total of 13 sextillion (1.3 × 1022) MOSFETs manufactured between 1960 and 2018.

N-type metal-oxide-semiconductor logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off, triode, saturation, and velocity saturation.

CMOS Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of MOSFET fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

Flash memory Electronic non-volatile computer storage device

Flash memory is an electronic (solid-state) non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory are named after the NAND and NOR logic gates. The individual flash memory cells, consisting of floating-gate MOSFETs, exhibit internal characteristics similar to those of the corresponding gates.

Static random-access memory Semiconductor memory

Static random-access memory is a type of semiconductor random-access memory (RAM) that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.

Dynamic random-access memory random-access memory that stores each bit of data in a separate capacitor within an integrated circuit

Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.

Reading is an action performed by computers, to acquire data from a source and place it into their volatile memory for processing. Computers may read information from a variety of sources, such as magnetic storage, the Internet, or audio and video input ports. Reading is one of the core functions of a Turing machine.

In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family. Many logic families were produced as individual components, each containing one or a few related basic logical functions, which could be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated circuits. A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption and delay.

Semiconductor memory is a digital electronic semiconductor device used for digital data storage, such as computer memory. It typically refers to MOS memory, where data is stored within metal–oxide–semiconductor (MOS) memory cells on a silicon integrated circuit memory chip. There are numerous different types of implementations using various MOS technologies. The two main types of random-access memory (RAM) are static RAM (SRAM), which uses several MOSFETs per memory cell, and dynamic RAM (DRAM), which uses a single MOSFET and MOS capacitor per cell. Non-volatile memory uses floating-gate memory cells, which consist of a single floating-gate MOSFET per cell.

Ferroelectric RAM electronic device using the ferroelectric effect to produce low density random access memory

Ferroelectric RAM is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory.

Transistor count the number of transistors in a device

The transistor count is the number of transistors on an integrated circuit (IC). It typically refers to the number of MOSFETs on an IC chip, as all modern ICs use MOSFETs. It is the most common measure of IC complexity. The rate at which MOS transistor counts have increased generally follows Moore's law, which observed that the transistor count doubles approximately every two years.

The floating-gate MOSFET (FGMOS), also known as a floating-gate transistor, is a type of MOSFET where the gate is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify the amount of charge stored in the FG.

Charge trap flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. It is a type of floating-gate MOSFET memory technology, but differs from the conventional floating-gate technology in that it uses a silicon nitride film to store electrons rather than the doped polycrystalline silicon typical of a floating-gate structure. This approach allows memory manufacturers to reduce manufacturing costs five ways:

  1. Fewer process steps are required to form a charge storage node
  2. Smaller process geometries can be used
  3. Multiple bits can be stored on a single flash memory cell.
  4. Improved reliability
  5. Higher yield since the charge trap is less susceptible to point defects in the tunnel oxide layer

SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"silicon dioxide"—"silicon", is a cross sectional structure of MOSFET (metal-oxide-semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977. This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays. It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material. A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon"). Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia.

PMOS logic p-type MOSFETs to implement logic gates

P-type metal-oxide-semiconductor logic uses p-channel (+) metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-type transistor body. This inversion layer, called the p-channel, can conduct holes between p-type "source" and "drain" terminals.

In electronics, a multi-level cell (MLC) is a memory cell/element capable of storing more than a single bit of information, compared to a single-level cell (SLC) which can store only one bit per memory cell/element. A memory cell typically consists of a single MOSFET, thus multi-level cells reduce the number of MOSFETs required to store the same amount of data as single-level cells.

Random-access memory Form of computer data storage

Random-access memory is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.

In modern computer memory, a sense amplifier is one of the elements which make up the circuitry on a semiconductor memory chip ; the term itself dates back to the era of magnetic core memory. A sense amplifier is part of the read circuitry that is used when data is read from the memory; its role is to sense the low power signals from a bitline that represents a data bit stored in a memory cell, and amplify the small voltage swing to recognizable logic levels so the data can be interpreted properly by logic outside the memory.


  1. D. Tang, Denny; Lee, Yuan-Jen (2010). Magnetic Memory: Fundamentals and Technology. Cambridge University Press. p. 91. ISBN   978-1139484497 . Retrieved 13 December 2015.
  2. Fletcher, William (1980). An engineering approach to digital design . Prentice-Hall. p.  283. ISBN   0-13-277699-5.
  3. Microelectronic Circuits (Second ed.). Holt, Rinehart and Winston, Inc. 1987. p.  883. ISBN   0-03-007328-6.
  4. "La Question Technique : le cache, comment ça marche ?". PC World Fr. Archived from the original on 2014-03-30.
  5. O’Regan, Gerard (2013). Giants of Computing: A Compendium of Select, Pivotal Pioneers. Springer Science & Business Media. p. 267. ISBN   978-1447153405 . Retrieved 13 December 2015.
  6. Reilly, Edwin D. (2003). Milestones in Computer Science and Information Technology. Greenwood Publishing Group. p. 164. ISBN   9781573565219.
  7. W. Pugh, Emerson; R. Johnson, Lyle; H. Palmer, John (1991). IBM's 360 and Early 370 Systems. MIT Press. p. 706. ISBN   0262161230 . Retrieved 9 December 2015.
  8. "1953: Whirlwind computer debuts core memory". Computer History Museum . Retrieved 2 August 2019.
  9. Taylor, Alan (18 June 1979). Computerworld: Mass. Town has become computer capital. IDG Enterprise. p. 25.
  10. "1966: Semiconductor RAMs Serve High-speed Storage Needs". Computer History Museum . Retrieved 19 June 2019.
  11. "1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum.
  12. "Transistors - an overview". ScienceDirect . Retrieved 8 August 2019.
  13. 1 2 3 "1970: Semiconductors compete with magnetic cores". Computer History Museum . Retrieved 19 June 2019.
  14. Solid State Design - Vol. 6. Horizon House. 1965.
  15. 1 2 "Late 1960s: Beginnings of MOS memory" (PDF). Semiconductor History Museum of Japan. 2019-01-23. Retrieved 27 June 2019.
  16. "Spec Sheet for Toshiba "TOSCAL" BC-1411". Old Calculator Web Museum. Archived from the original on 3 July 2017. Retrieved 8 May 2018.
  17. Toshiba "Toscal" BC-1411 Desktop Calculator Archived 2007-05-20 at the Wayback Machine
  18. "DRAM". IBM100. IBM. 9 August 2017. Retrieved 20 September 2019.
  19. "Robert Dennard". Encyclopedia Britannica . Retrieved 8 July 2019.
  20. Kent, Allen; Williams, James G. (6 January 1992). Encyclopedia of Microcomputers: Volume 9 - Icon Programming Language to Knowledge-Based Systems: APL Techniques. CRC Press. p. 131. ISBN   9780824727086.
  21. "1963: Complementary MOS Circuit Configuration is Invented". Computer History Museum . Retrieved 6 July 2019.
  22. 1 2 "1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor History Museum of Japan. Retrieved 5 July 2019.
  23. 1 2 3 "Memory". STOL (Semiconductor Technology Online). Retrieved 25 June 2019.
  24. "1980s: DRAM capacity increases, the shift to CMOS advances, and Japan dominates the market" (PDF). Semiconductor History Museum of Japan. Retrieved 19 July 2019.
  25. D. Kahng and S. M. Sze, "A floating-gate and its application to memory devices", The Bell System Technical Journal, vol. 46, no. 4, 1967, pp. 1288–1295
  26. "1971: Reusable semiconductor ROM introduced". Computer History Museum . Retrieved 19 June 2019.
  27. 1 2 3 Bez, R.; Pirovano, A. (2019). Advances in Non-Volatile Memory and Storage Technology. Woodhead Publishing. ISBN   9780081025857.
  28. Fulford, Benjamin (24 June 2002). "Unsung hero". Forbes. Archived from the original on 3 March 2008. Retrieved 18 March 2008.
  29. US 4531203 Fujio Masuoka
  30. "Toshiba: Inventor of Flash Memory". Toshiba . Retrieved 20 June 2019.
  31. Masuoka, F.; Momodomi, M.; Iwata, Y.; Shirota, R. (1987). "New ultra high density EPROM and flash EEPROM with NAND structure cell". Electron Devices Meeting, 1987 International. IEDM 1987. IEEE. doi:10.1109/IEDM.1987.191485.
  32. "Toshiba announces new "3D" NAND flash technology". Engadget . 2007-06-12. Retrieved 10 July 2019.
  33. "Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications". Samsung Semiconductor Global Website.
  34. Clarke, Peter. "Samsung Confirms 24 Layers in 3D NAND". EE Times .
  35. Jacob, Bruce; Ng, Spencer; Wang, David (28 July 2010). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann. p. 355. ISBN   9780080553849.
  36. 1 2 Siddiqi, Muzaffer A. (19 December 2012). Dynamic RAM: Technology Advancements. CRC Press. p. 10. ISBN   9781439893739.
  37. 1 2 3 4 Li, Hai; Chen, Yiran (19 April 2016). Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. CRC Press. pp. 6, 7. ISBN   9781439807460.