High-level synthesis

Last updated

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. [1] Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages., [2] although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer level (RTL) design in a hardware description language (HDL), which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process. [3]

Contents

Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. [4] The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.

History

Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the finite-state machine. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path.

First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler [5] and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler. [6]

In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behavioral synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification. [7] Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.

High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States. [8]

Source input

The most common source inputs for high-level synthesis are based on standard languages such as ANSI C/C++, SystemC and MATLAB.

High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete. [9] Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations.

Process stages

The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution. [10]

Functionality

In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency.

Architectural constraints

Synthesis constraints for the architecture can automatically be applied based on the design analysis. [3] These constraints can be broken into

Interface synthesis

Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO. [11]

Vendors

Data reported on recent Survey [12]

StatusCompilerOwnerLicenseInputOutputYearDomainTest
Bench
FPFixP
In Use AUGH TIMA Lab.AcademicC subsetVHDL2012AllYesNoNo
eXCite Y ExplorationsCommercialCVHDL/Verilog2001AllYesNoYes
Bambu PoliMiAcademicCVHDL/Verilog2012AllYesYesNo
Bluespec BlueSpec Inc.CommercialBSVSystemVerilog2007AllNoNoNo
CHCAltiumCommercialC subsetVHDL/Verilog2008AllNoYesYes
CoDeveloperImpulse AcceleratedCommercialImpulse-CVHDL2003Image
Streaming
YesYesNo
HDL Coder MathWorksCommercialMATLAB, Simulink, Stateflow, SimscapeVHDL / Verilog2003Control Systems, Signal Processing, Wireless, Radar, Communications, Image and Computer VisionYesYesYes
StratusCadenceCommercialC/C++ SystemCRTL2015AllYesNoYes
CyberWorkbenchNECCommercialBDL, SystemCVHDL/Verilog2011AllCycle/
Formal
YesYes
CatapultMentor
(Siemens business)
CommercialC, C++, SystemCVHDL/Verilog2004StreamingNoNoYes
DWARVTU. DelftAcademicC subsetVHDL2012AllYesYesYes
GAUT U. BretagneAcademicC/C++VHDL2010DSPYesNoYes
Hastlayer Lombiq TechnologiesCommercialC#/C++/F#...
(.NET)
VHDL2015.NETYesYesYes
Instant SoC FPGA CoresCommercialC/C++VHDL/Verilog2019AllYesNoNo
Intel High Level Synthesis Compiler Intel FPGA (Formerly Altera)CommercialC/C++Verilog2017AllYesYesYes
LegUp HLS LegUp ComputingCommercialC/C++Verilog2017AllYesYesYes
LegUp U. TorontoAcademicCVerilog2011AllYesYesNo
MaxCompilerMaxelerCommercialMaxJRTL2010DataFlowNoYesNo
ROCCC Jacquard Comp.CommercialC subsetVHDL2010StreamingNoYesNo
Symphony CSynopsysCommercialC/C++VHDL/Verilog/
SystemC
2010AllYesNoYes
VivadoHLS
(formerly AutoPilot
from AutoESL [13] )
XilinxCommercialC/C++/SystemCVHDL/Verilog/
SystemC
2013AllYesYesYes
Kiwi U. CambridgeAcademicC#Verilog2008.NETNoYesYes
CHiMPSU. WashingtonAcademicCVHDL2008AllNoNoNo
gcc2verilogU. KoreaAcademicCVerilog2011AllNoNoNo
HercuLeSAjax CompilersCommercialC/NACVHDL2012AllYesYesYes
Shang ?U. IllinoisCVerilog2013AllYes??
TridentLos Alamos NLAcademicC subsetVHDL2007ScientificNoYesNo
Aban-
doned
AccelDSPXilinxCommercialMATLABVHDL/Verilog2006DSPYesYesYes
C2HAlteraCommercialCVHDL/Verilog2006AllNoNoNo
CtoVerilogU. HaifaAcademicCVerilog2008AllNoNoNo
DEFACTOU. South Cailf.AcademicCRTL1999DSENoNoNo
GarpU. BerkeleyAcademicC subsetbitstream2000LoopNoNoNo
MATCHU. NorthwestAcademicMATLABVHDL2000ImageNoNoNo
Napa-CSarnoff Corp.AcademicC subsetVHDL/Verilog1998LoopNoNoNo
PipeRenchU.Carnegie M.AcademicDILbistream2000StreamNoNoNo
SA-CU. ColoradoAcademicSA-CVHDL2003ImageNoNoNo
SeaCucumberU. Brigham Y.AcademicJavaEDIF2002AllNoYesYes
SPARKU. Cal. IrvineAcademicCVHDL2003ControlNoNoNo

See also

Related Research Articles

In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.

System on a chip type of integrated circuit

A system on chip is an integrated circuit that integrates all components of a computer or other electronic system. These components typically include a central processing unit (CPU), memory, input/output ports and secondary storage – all on a single substrate or microchip, the size of a coin. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions, depending on the application. As they are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are very common in the mobile computing and edge computing markets. Systems-on-chip are typically fabricated using metal–oxide–semiconductor (MOS) technology, and are commonly used in embedded systems and the Internet of Things.

Reconfigurable computing is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow. On the other hand, the main difference from custom hardware, i.e. application-specific integrated circuits (ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design.

In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.

Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.

In electronics, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

Hardware emulation Emulating hardware devices in IC design

In integrated circuit design, hardware emulation is the process of imitating the behavior of one or more pieces of hardware with another piece of hardware, typically a special purpose emulation system. The emulation model is usually based on a hardware description language source code, which is compiled into the format used by emulation system. The goal is normally debugging and functional verification of the system being designed. Often an emulator is fast enough to be plugged into a working target system in place of a yet-to-be-built chip, so the whole system can be debugged with live data. This is a specific case of in-circuit emulation.

Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, an EDA-industry-analysis firm, on February 1, 2001. It is defined in ESL Design and Verification as: "the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner."

Intel Quartus Prime is programmable logic device design software produced by Intel; prior to Intel's acquisition of Altera the tool was called Altera Quartus II. Quartus Prime enables analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus Prime includes an implementation of VHDL and Verilog for hardware description, visual editing of logic circuits, and vector waveform simulation.

Jingsheng Jason Cong is a Chinese-born American computer scientist, educator, and serial entrepreneur. He received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. He has been on the faculty in the Computer Science Department at the University of California, Los Angeles (UCLA) since 1990. Currently, he is a Distinguished Chancellor’s Professor and the director of Center for Domain-Specific Computing (CDSC).

C to HDL tools convert C language or C-like computer code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array. Compared to software, equivalent designs in hardware consume less power and execute faster with lower latency, more parallelism and higher throughput. However, system design and functional verification in a hardware description language can be tedious and time-consuming, so systems engineers often write critical modules in HDL and other modules in a high-level language and synthesize these into HDL through C to HDL or high-level synthesis tools.

Graphical system design (GSD) is a modern approach to designing measurement and control systems that integrates system design software with COTS hardware to dramatically simplify development. This approach combines user interfaces, models of computation, math and analysis, Input/output signals, technology abstractions, and various deployment target. It allows domain experts, or non- implementation experts, to access to design capabilities where they would traditionally need to outsource a system design expert.

Forte Design Systems, Inc. is a San Jose, CA, based provider of high-level synthesis (HLS) software products, also known as electronic system-level (ESL) synthesis. Forte's main product is Cynthesizer. On February 14, 2014, Forte was acquired by Cadence Design Systems. Terms of the transaction were not disclosed.

Verilator

Verilator is a free and open-source software tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. It is restricted to modeling the synthesizable subset of Verilog and the generated models are cycle-accurate, 2-state, with synthesis semantics. As a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can process the entire Verilog language and model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.

Catapult C Synthesis, a commercial electronic design automation product of Mentor Graphics, is a high-level synthesis tool, sometimes called algorithmic synthesis or ESL synthesis. Catapult C takes ANSI C/C++ and SystemC inputs and generates register transfer level (RTL) code targeted to FPGAs and ASICs.

High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis, HLV is to HLS as functional verification is to logic synthesis.

EVE/ZeBu

EVE/ZeBu is a provider of hardware-assisted verification tools for functional verification of Application-specific integrated circuits (ASICs) and system on chip (SOC) designs and for validation of embedded software ahead of implementation in silicon. EVE's hardware acceleration and hardware emulation products work in conjunction with Verilog, SystemVerilog, and VHDL-based simulators from Synopsys, Cadence Design Systems and Mentor Graphics. EVE's flagship product is ZeBu.

Xilinx Vivado

Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of HDL designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis. Vivado represents a ground-up rewrite and re-thinking of the entire design flow, and has been described by reviewers as "well conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive".

VisualSim Architect

VisualSim Architect is an electronic system-level software for modeling and simulation of electronic systems, embedded software and semiconductors. VisualSim Architect is a commercial version of the Ptolemy II research project at University of California Berkeley. The product was first released in 2003. VisualSim is a graphical tool that can be used for performance trade-off analyses using such metrics as bandwidth utilization, application response time and buffer requirements. It can be used for architectural analysis of algorithms, components, software instructions and hardware/ software partitioning.

References

  1. "High-Level Synthesis - Springer". Springerlink.com. Retrieved 2016-10-03.
  2. IEEE Xplore High-Level Synthesis: Past, Present, and Future DOI 10.1109/MDT.2009.83
  3. 1 2 "The 'why' and 'what' of algorithmic synthesis". EE Times. Retrieved 2016-10-03.
  4. "C-Based Rapid Prototyping for Digital Signal Processing" (PDF). UBS University, France. Retrieved 2016-10-03.
  5. "Publications and Presentations". Bdti.com. Archived from the original on 2008-04-26. Retrieved 2016-10-03.
  6. "Behavioral synthesis crossroad". EE Times. Retrieved 2016-10-03.
  7. [ dead link ]
  8. Multiple Word-Length High-Level Synthesis EURASIP Journal on Embedded Systems
  9. "A look inside behavioral synthesis". EE Times. Retrieved 2016-10-03.
  10. Nane, R.; Sima, V. M.; Pilato, C.; Choi, J.; Fort, B.; Canis, A.; Chen, Y. T.; Hsiao, H.; Brown, S. (2016). "A Survey and Evaluation of FPGA High-Level Synthesis Tools" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35 (10): 1591–1604. doi:10.1109/TCAD.2015.2513673. hdl:11311/998432. ISSN   0278-0070.
  11. "Xilinx buys high-level synthesis EDA vendor". EE Times. 2011-02-05. Archived from the original on 2011-10-17. Retrieved 2016-10-03.
  12. "MathWorks – Makers of MATLAB and Simulink". Mathworks.com. Retrieved 2016-10-03.
  13. "SystemC based ESL methodologies - SystemC based ESL methodologies". Circuitsutra.com. Retrieved 2016-10-03.
  14. John M. at a major ERP & DBMS Corporation (2016-08-29). "QuickPlay: Bringing FPGA Computing to the Masses". Quickplay.io. Retrieved 2016-10-03.
  15. "CyberWorkBench: Products". NEC. Retrieved 2016-10-03.
  16. "Nikolaos Kavvadias - HercuLeS high-level synthesis tool". Nkavvadias.com. Retrieved 2016-10-03.
  17. "Synopsys buys Synfora assets". EE Times. Archived from the original on 2011-04-07. Retrieved 2016-10-03.
  18. "The xPilot System". Cadlab.cs.ucla.edu. Retrieved 2016-10-03.
  19. "vSyn.ru". vSyn.ru. 2016-06-16. Archived from the original on 2016-06-30. Retrieved 2016-10-03.
  20. "Hardware design for all". Synflow. Retrieved 2016-10-03.

Further reading