High-level synthesis

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High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. [1] Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages., [2] although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer level (RTL) design in a hardware description language (HDL), which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process. [3]


Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. [4] The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.


Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the finite-state machine. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path.

First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler [5] and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler. [6]

In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behavioral synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification. [7] Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.

High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States. [8]

Source input

The most common source inputs for high-level synthesis are based on standard languages such as ANSI C/C++, SystemC and MATLAB.

High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete. [9] Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations.

Process stages

The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution. [10]


In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency.

Architectural constraints

Synthesis constraints for the architecture can automatically be applied based on the design analysis. [3] These constraints can be broken into

Interface synthesis

Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO. [11]


Data reported on recent Survey [12]

In Use AUGH TIMA Lab.AcademicC subsetVHDL2012AllYesNoNo
eXCite Y ExplorationsCommercialCVHDL/Verilog2001AllYesNoYes
Bambu PoliMiAcademicCVHDL/Verilog2012AllYesYesNo
Bluespec BlueSpec Inc.CommercialBSVSystemVerilog2007AllNoNoNo
CHCAltiumCommercialC subsetVHDL/Verilog2008AllNoYesYes
CoDeveloperImpulse AcceleratedCommercialImpulse-CVHDL2003Image
HDL Coder MathWorksCommercialMATLAB, Simulink, Stateflow, SimscapeVHDL / Verilog2003Control Systems, Signal Processing, Wireless, Radar, Communications, Image and Computer VisionYesYesYes
StratusCadenceCommercialC/C++ SystemCRTL2015AllYesNoYes
CyberWorkbenchNECCommercialBDL, SystemCVHDL/Verilog2011AllCycle/
(Siemens business)
CommercialC, C++, SystemCVHDL/Verilog2004StreamingNoNoYes
DWARVTU. DelftAcademicC subsetVHDL2012AllYesYesYes
GAUT U. BretagneAcademicC/C++VHDL2010DSPYesNoYes
Hastlayer Lombiq TechnologiesCommercialC#/C++/F#...
Instant SoC FPGA CoresCommercialC/C++VHDL/Verilog2019AllYesNoNo
Intel High Level Synthesis Compiler Intel FPGA (Formerly Altera)CommercialC/C++Verilog2017AllYesYesYes
LegUp HLS LegUp ComputingCommercialC/C++Verilog2017AllYesYesYes
LegUp U. TorontoAcademicCVerilog2011AllYesYesNo
ROCCC Jacquard Comp.CommercialC subsetVHDL2010StreamingNoYesNo
Symphony CSynopsysCommercialC/C++VHDL/Verilog/
(formerly AutoPilot
from AutoESL [13] )
Kiwi U. CambridgeAcademicC#Verilog2008.NETNoYesYes
CHiMPSU. WashingtonAcademicCVHDL2008AllNoNoNo
gcc2verilogU. KoreaAcademicCVerilog2011AllNoNoNo
HercuLeSAjax CompilersCommercialC/NACVHDL2012AllYesYesYes
Shang ?U. IllinoisCVerilog2013AllYes??
TridentLos Alamos NLAcademicC subsetVHDL2007ScientificNoYesNo
CtoVerilogU. HaifaAcademicCVerilog2008AllNoNoNo
DEFACTOU. South Cailf.AcademicCRTL1999DSENoNoNo
GarpU. BerkeleyAcademicC subsetbitstream2000LoopNoNoNo
MATCHU. NorthwestAcademicMATLABVHDL2000ImageNoNoNo
Napa-CSarnoff Corp.AcademicC subsetVHDL/Verilog1998LoopNoNoNo
PipeRenchU.Carnegie M.AcademicDILbistream2000StreamNoNoNo
SA-CU. ColoradoAcademicSA-CVHDL2003ImageNoNoNo
SeaCucumberU. Brigham Y.AcademicJavaEDIF2002AllNoYesYes
SPARKU. Cal. IrvineAcademicCVHDL2003ControlNoNoNo

See also

Related Research Articles

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Further reading