Synopsys

Last updated
Synopsys, Inc.
Public
Traded as
ISIN US8716071076  OOjs UI icon edit-ltr-progressive.svg
Industry
PredecessorC Level Design  OOjs UI icon edit-ltr-progressive.svg
Founded1986 in Research Triangle Park, North Carolina.
FounderDavid Gregory
Aart de Geus
Headquarters Mountain View, California, U.S.
Key people
Aart J. de Geus
(Founder, Chairman & co-CEO)
Chi-Foon Chan
(President & co-CEO)
RevenueIncrease2.svg US$3.3 billion (2019) [1]
Increase2.svg US$625 million (2019) [1]
Number of employees
13,000 [2]
Divisions Silicon Design & Verification, Silicon Intellectual Property, Software Integrity Group
Website synopsys.com

Synopsys ( /sɪˈnɒpsɪs/ ) is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators, as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems. In recent years, Synopsys has expanded its products and services to include application security testing. Their technology is present in self-driving cars, artificial intelligence, and internet of things consumer products.

Contents

History

Synopsys was founded by Aart J de Geus and David Gregory in 1986 in Research Triangle Park, North Carolina. The outfit was initially established as Optimal Solutions with a charter to develop and market synthesis technology developed by the team at General Electric. They have evolved to become a leader in electronic design automation, semiconductor intellectual property, and software security solutions.[ citation needed ]

Divisions

Synopsys has three divisions including silicon design and verification, silicon intellectual property, and software integrity.

Silicon Design & Verification

This Synopsys division focuses the design and verification of integrated circuits and designing more advanced processes and models for the manufacturing of those chips. [3]

Silicon Intellectual Property

This division of Synopsys focuses on the enabling organizations to create high-quality silicon proven intellectual property solutions for System on a chip (SoC) designs. [4]

Software Integrity

In 2014, Synopsys began to expand their products and services to include software security and quality. This division helps organizations integrate security into DevOps environments, build holistic application security programs, test any software on-demand, find and fix software quality and compliance issues earlier, identify and manage open source components, and assess application security threats, risks and dependancies. [5]

Products

Synopsys has three types of products and services within the three divisions of Silicon Design & Verification [6] , Silicon Intellectual Property [7] , and Software Integrity. [8] Synopsys has a number of products and services, including:

See also

Related Research Articles

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In electronics, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

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The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM which was, to a large part, based on the eRM for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, and Synopsys.

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References

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  2. "Synopsys Corporate Backgrounder Spring 2018" (PDF). Synopsys.com. Retrieved 2019-11-06.
  3. "Electronic Design Automation (EDA)". www.synopsys.com. Retrieved 2020-02-03.
  4. "Synopsys DesignWare IP". www.synopsys.com. Retrieved 2020-02-03.
  5. "Synopsys Security | Software Integrity Group". www.synopsys.com. Retrieved 2020-02-03.
  6. "Electronic Design Automation (EDA)". www.synopsys.com. Retrieved 2019-07-15.
  7. "IP Accelerated Synopsys" (PDF). Synopsys.com. 2019-11-02.
  8. "Software Security & Quality Tools & Services | Synopsys". www.synopsys.com. Retrieved 2019-06-07.
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