Libre-SOC

Last updated
Libre-SOC
LibreSOC prototype in MQFP.jpg
LibreSOC prototype in 128-pin MQFP
General information
Launched2019-08-29 [1]
Designed byLuke Leighton, Libre-SOC Team
Common manufacturer
Architecture and classification
Application Soft core
Technology node 180 nm
Instruction set Power ISA 3.0
ppc64le
ppc64be
Physical specifications
Cores
  • 1

Libre-SOC was a project by Luke Leighton and other contributors to build a libre soft processor core, announced at the OpenPOWER Summit NA 2020. [2] It adhered to the Power ISA 3.0 instruction set and could be run on field-programmable gate array boards, currently booting MicroPython and other bare-metal applications.

Contents

The purpose of Libre-SOC was to be a system on a chip (SoC) with 3D and video capability built-in as part of the Power ISA, suitable for single-board computers, netbooks, IoT devices and other small form factors, while retaining a completely free and open design. [3]

On June 23, 2024 Luke Leighton described the project as "effectively terminated"

History

Libre-SOC began its life when Luke Leighton wanted there to be a completely free and libre system on a chip offering. He initially opted for a RISC-V base, but later switched to OpenPOWER when that seemed like a better fit for the project. [4] [5] It is the second processor written from scratch using the OpenPOWER ISA 3.0, and the first libre core that is completely independent of IBM.

The project is mostly funded through NLnet grants. [6] [7]

While being developed as a "soft core" Libre-SOC will be fabricated in 180 nm by TSMC's "Open MPW Shuttle Program" through IMEC in 2021. [8] The finished ASIC was sent to IMEC in July 2021. [9]

Design

Libre-SOC is a 64-bit bi-endian scalar processor core, implementing a subset of the Power ISA 3.0 instruction set. It has 32× 64-bit general purpose registers. It uses Wishbone for the memory interface.

The Libre-SOC core will be a hybrid design, based around a precise-augmented version of the historic CDC 6600 microarchitecture, [10] merging traditional general purpose, vector and graphics computing into a single execution unit reducing complexity and size of the complete chip as well as simplifying 3D driver development. [11] This constitutes the need to add a small addition to the OpenPOWER instruction set architecture called "Simple-V". [12] [13] SVP64, currently in draft, [14] extends OpenPOWER register files to 128, including CR fields, in order to cope with modern 3D and Video workloads, effectively making Libre-SOC a Vector processor.

Like Microwatt, the initial development was done in around three months, included the entire integer processing functionality of the instruction set; the bare minimum to make it compliant, with no memory management unit and no floating-point unit. Libre-SOC's rapid development is, like Microwatt, down to the significant use of software engineering practices including thousands of unit tests [15] and by Microwatt source code as a reference design.

Libre-SOC is unusual in that it is designed using nMigen, a Python-based hardware description language (HDL). Also, to retain full transparency associated with "libre", the ASIC layout [16] is performed with coriolis2, a VLSI toolchain developed and maintained by Sorbonne University's Laboratoire d'Informatique de Paris 6.

See also

References

  1. ↑ Williams, Chris (2019-08-29). "Get your royalty-free soft-core OpenPOWER processor core blueprints here. Extra, extra – read all about it". The Register .
  2. ↑ OpenPOWER Summit NA 2020: The LibreSOC Initiative: a hybrid CPU/VPU/GPU
  3. ↑ Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source
  4. ↑ The Libre RISC-V Vulkan Accelerator Will Be Targeting 25 FPS @ 720p, 5~6 GFLOPs
  5. ↑ LibreSOC Still Striving To Produce An Open-Source Hybrid CPU/GPU Built On OpenPOWER
  6. ↑ The Libre-RISCV SoC
  7. ↑ NLNet Grants approved, Power ISA under consideration
  8. ↑ Libre-SOC 180nm ASIC plan
  9. ↑ "Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication". openpowerfoundation.org. Archived from the original on 8 July 2021. Retrieved 26 July 2023.
  10. ↑ 6600 scoreboard architecture
  11. ↑ XDC2020 Libre-SOC talk
  12. ↑ Simple-V Vectorisation for the OpenPOWER ISA
  13. ↑ The LibreSOC Project: Simple-V Vectorisation. Why we decided to invent a new Vector system on top of OpenPOWER
  14. ↑ SVP64 Draft Specification
  15. ↑ OpenPOWER ISA unit tests
  16. ↑ Libre-SOC git repository for GDS-II layout
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