Libre-SOC

Last updated
Libre-SOC
LibreSOC prototype in MQFP.jpg
LibreSOC prototype in 128-pin MQFP
General information
Launched2019-08-29 [1]
Designed byLuke Leighton, Libre-SOC Team
Common manufacturer
Architecture and classification
Application Soft core
Technology node 180 nm
Instruction set Power ISA 3.0
ppc64le
ppc64be
Physical specifications
Cores
  • 1

Libre-SOC is a libre soft processor core originally written by Luke Leighton and other contributors, announced at the OpenPOWER Summit NA 2020. [2] It adheres to the Power ISA 3.0 instruction set and can be run on field-programmable gate array boards, currently booting MicroPython and other bare-metal applications.

Contents

The purpose of Libre-SOC is to be a system on a chip (SoC) with 3D and video capability built-in as part of the Power ISA, suitable for single-board computers, netbooks, IoT devices and other small form factors, while retaining a completely free and open design. [3]

On June 23, 2024 Luke Leighton described the project as "effectively terminated"

History

Libre-SOC began its life when Luke Leighton wanted there to be a completely free and libre system on a chip offering. He initially opted for a RISC-V base, but later switched to OpenPOWER when that seemed like a better fit for the project. [4] [5] It is the second processor written from scratch using the OpenPOWER ISA 3.0, and the first libre core that is completely independent of IBM.

The project is mostly funded through NLnet grants. [6] [7]

While being developed as a "soft core" Libre-SOC will be fabricated in 180 nm by TSMC's "Open MPW Shuttle Program" through Imec in 2021. [8] The finished ASIC was sent to Imec in July 2021. [9]

Design

Libre-SOC is a 64-bit bi-endian scalar processor core, implementing a subset of the Power ISA 3.0 instruction set. It has 32× 64-bit general purpose registers. It uses Wishbone for the memory interface.

The Libre-SOC core will be a hybrid design, based around a precise-augmented version of the historic CDC 6600 microarchitecture, [10] merging traditional general purpose, vector and graphics computing into a single execution unit reducing complexity and size of the complete chip as well as simplifying 3D driver development. [11] This constitutes the need to add a small addition to the OpenPOWER instruction set architecture called "Simple-V". [12] [13] SVP64, currently in draft, [14] extends OpenPOWER register files to 128, including CR fields, in order to cope with modern 3D and Video workloads, effectively making Libre-SOC a Vector processor.

Like Microwatt, the initial development was done in around three months, included the entire integer processing functionality of the instruction set; the bare minimum to make it compliant, with no memory management unit and no floating-point unit. Libre-SOC's rapid development is, like Microwatt, down to the significant use of software engineering practices including thousands of unit tests [15] and by Microwatt source code as a reference design.

Libre-SOC is unusual in that it is designed using nMigen, a Python-based hardware description language (HDL). Also, to retain full transparency associated with "libre", the ASIC layout [16] is performed with coriolis2, a VLSI toolchain developed and maintained by Sorbonne University's Laboratoire d'Informatique de Paris 6.

Hardware implementation

LibreSOC samples in tray. Photograph taken at their archival place in LIP6/Jussieu in 2024. LibreSOC M7 7953 2513px.jpg
LibreSOC samples in tray. Photograph taken at their archival place in LIP6/Jussieu in 2024.

While Libre-SOC is as developed as a libre software project, eventually the goal is to produce real "hard" hardware products as opposed to the "soft" synthesised versions that reflects the actual development.

The first hard version of the Libre-SOC is fabricated by TSMC on their 180 nm node. The chip comprises 130.000 logic gates, measures 5.5 × 5.9 mm2 and will be packaged in a 128 pin QFP package. [9]

See also

Related Research Articles

<span class="mw-page-title-main">Reduced instruction set computer</span> Processor executing one instruction in minimal clock cycles

In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler to achieve given simpler instructions.

In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set where its instructions are designed to operate efficiently and effectively on large one-dimensional arrays of data called vectors. This is in contrast to scalar processors, whose instructions operate on single data items only, and in contrast to some of those same scalar processors having additional single instruction, multiple data (SIMD) or SIMD within a register (SWAR) Arithmetic Units. Vector processors can greatly improve performance on certain workloads, notably numerical simulation and similar tasks. Vector processing techniques also operate in video-game console hardware and in graphics accelerators.

SuperH is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.

<span class="mw-page-title-main">Graphics processing unit</span> Specialized electronic circuit; graphics accelerator

A graphics processing unit (GPU) is a specialized electronic circuit initially designed for digital image processing and to accelerate computer graphics, being present either as a discrete video card or embedded on motherboards, mobile phones, personal computers, workstations, and game consoles. After their initial design, GPUs were found to be useful for non-graphic calculations involving embarrassingly parallel problems due to their parallel structure. Other non-graphical uses include the training of neural networks and cryptocurrency mining.

OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.

<span class="mw-page-title-main">Hardware acceleration</span> Specialized computer hardware

Hardware acceleration is the use of computer hardware designed to perform specific functions more efficiently when compared to software running on a general-purpose central processing unit (CPU). Any transformation of data that can be calculated in software running on a generic CPU can also be calculated in custom-made hardware, or in some mix of both.

<span class="mw-page-title-main">FR-V (microprocessor)</span>

The Fujitsu FR-V is one of the very few processors ever able to process both a very long instruction word (VLIW) and vector processor instructions at the same time, increasing throughput with high parallel computing while increasing performance per watt and hardware efficiency. The family was presented in 1999. Its design was influenced by the VPP500/5000 models of the Fujitsu VP/2000 vector processor supercomputer line.

The transistor count is the number of transistors in an electronic device. It is the most common measure of integrated circuit complexity. The rate at which MOS transistor counts have increased generally follows Moore's law, which observes that transistor count doubles approximately every two years. However, being directly proportional to the area of a die, transistor count does not represent how advanced the corresponding manufacturing technology is. A better indication of this is transistor density which is the ratio of a semiconductor's transistor count to its die area.

An application-specific instruction set processor (ASIP) is a component used in system on a chip design. The instruction set architecture of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose central processing unit (CPU) and the performance of an application-specific integrated circuit (ASIC).

Project Denver is the codename of a central processing unit designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128 MB cache stored in main memory". Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores into one die constituting a system on a chip (SoC).

IBM POWER is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC.

IBM Power microprocessors are designed and sold by IBM for servers and supercomputers. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The Power line of microprocessors has been used in IBM's RS/6000, AS/400, pSeries, iSeries, System p, System i, and Power Systems lines of servers and supercomputers. They have also been used in data storage devices and workstations by IBM and by other server manufacturers like Bull and Hitachi.

The OpenPOWER Foundation is a collaboration around Power ISA-based products initiated by IBM and announced as the "OpenPOWER Consortium" on August 6, 2013. IBM's focus is to open up technology surrounding their Power Architecture offerings, such as processor specifications, firmware, and software with a liberal license, and will be using a collaborative development model with their partners.

Heterogeneous computing refers to systems that use more than one kind of processor or core. These systems gain performance or energy efficiency not just by adding the same type of processors, but by adding dissimilar coprocessors, usually incorporating specialized processing capabilities to handle particular tasks.

RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 2019. Like several other RISC ISAs, e.g. Amber (ARMv2) or OpenRISC, RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD License.

<span class="mw-page-title-main">SiFive</span> Fabless semiconductor company providing RISC-V processors

SiFive, Inc. is an American fabless semiconductor company and provider of commercial RISC-V processors and silicon chips based on the RISC-V instruction set architecture (ISA). Its products include cores, SoCs, IPs, and development boards.

<span class="mw-page-title-main">Power ISA</span> Computer instruction set architecture

Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor.

The Pixel Visual Core (PVC) is a series of ARM-based system in package (SiP) image processors designed by Google. The PVC is a fully programmable image, vision and AI multi-core domain-specific architecture (DSA) for mobile devices and in future for IoT. It first appeared in the Google Pixel 2 and 2 XL which were introduced on October 19, 2017. It has also appeared in the Google Pixel 3 and 3 XL. Starting with the Pixel 4, this chip was replaced with the Pixel Neural Core.

<span class="mw-page-title-main">Zen 3</span> 2020 AMD 7-nanometer processor microarchitecture

Zen 3 is the name for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process for the chiplets and GlobalFoundries's 14 nm process for the I/O die on the server chips and 12 nm for desktop chips. Zen 3 powers Ryzen 5000 mainstream desktop processors and Epyc server processors. Zen 3 is supported on motherboards with 500 series chipsets; 400 series boards also saw support on select B450 / X470 motherboards with certain BIOSes. Zen 3 is the last microarchitecture before AMD switched to DDR5 memory and new sockets, which are AM5 for the desktop "Ryzen" chips alongside SP5 and SP6 for the EPYC server platform and sTRX8. According to AMD, Zen 3 has a 19% higher instructions per cycle (IPC) on average than Zen 2.

Microwatt is an open source soft processor core originally written in VHDL by Anton Blanchard at IBM, announced at the OpenPOWER Summit NA 2019 and published on GitHub in August 2019. It adheres to the Power ISA 3.0 instruction set and can be run on FPGA boards, booting Linux, MicroPython and Zephyr.

References

  1. ↑ Williams, Chris (2019-08-29). "Get your royalty-free soft-core OpenPOWER processor core blueprints here. Extra, extra – read all about it". The Register .
  2. ↑ OpenPOWER Summit NA 2020: The LibreSOC Initiative: a hybrid CPU/VPU/GPU
  3. ↑ Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source
  4. ↑ The Libre RISC-V Vulkan Accelerator Will Be Targeting 25 FPS @ 720p, 5~6 GFLOPs
  5. ↑ LibreSOC Still Striving To Produce An Open-Source Hybrid CPU/GPU Built On OpenPOWER
  6. ↑ The Libre-RISCV SoC
  7. ↑ NLNet Grants approved, Power ISA under consideration
  8. ↑ Libre-SOC 180nm ASIC plan
  9. 1 2 "Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication". openpowerfoundation.org. Archived from the original on 8 July 2021. Retrieved 26 July 2023.
  10. ↑ 6600 scoreboard architecture
  11. ↑ XDC2020 Libre-SOC talk
  12. ↑ Simple-V Vectorisation for the OpenPOWER ISA
  13. ↑ The LibreSOC Project: Simple-V Vectorisation. Why we decided to invent a new Vector system on top of OpenPOWER
  14. ↑ SVP64 Draft Specification
  15. ↑ OpenPOWER ISA unit tests
  16. ↑ Libre-SOC git repository for GDS-II layout
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.