|Designer||Damjan Lampret, with contributions from OpenRISC community members|
|Endianness||Big (unimplemented stub for Little)|
|Open||Yes, and royalty free|
|General purpose||16 or 32|
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computing (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32- and 64-bit processors with optional floating point and vector processing support,and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL).
The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL).
A reference system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs),and there have been several commercial derivatives produced.
The instruction set is a reasonably simple MIPS architecture-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.
Another notable feature is a rich set of single instruction, multiple data (SIMD) instructions intended for digital signal processing.
Most implementations are on field-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance.
As the OpenRISC 1000 is now considered stable, ORSoC (owner of OpenCores) launched a crowd-funding project trying to build a cost-efficient application-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community.[ citation needed ] The project never reached the goal.
As of April 2017 [update] , no open-source ASIC had been produced.
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which can run both the OpenRISC 1000 and BA12. Flextronics (Flex) and Jennic Limited manufactured the OpenRISC as part of an application-specific integrated circuit (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series).Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.
Cadence Design Systems have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera).
TechEdSat, the first NASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.
The OpenRISC community have ported the GNU toolchain to OpenRISC to support development in the programming languages C and C++. Using this toolchain the newlib, uClibc, musl (as of release 1.1.4), and glibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical integrated development environment (IDE) based on this toolchain. A project to port LLVM to the OpenRISC 1000 architecture began in early 2012.
GCC 9 released with OpenRISC support.
The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is a register-transfer level (RTL) model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see OVPsim), set up by Imperas.
The mainline Linux kernel gained support for OpenRISC in version 3.1.The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k). Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.
Several real-time operating systems (RTOS) have been ported to OpenRISC, including RTEMS, FreeRTOS, and eCos.
Since version 1.2, QEMU supports emulating OpenRISC platforms.
SPARC is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems and Fujitsu. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from a number of vendors through the 1980s and 90s.
ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures—including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products.
SuperH is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 64-bit microcomputers are computers in which 64-bit microprocessors are the norm. From the software perspective, 64-bit computing means the use of code with 64-bit virtual memory addresses. However, not all 64-bit instruction sets support full 64-bit virtual memory addresses; x86-64 and ARMv8, for example, support only 48 bits of virtual address, with the remaining 16 bits of the virtual address required to be all 0's or all 1's, and several 64-bit instruction sets support fewer than 64 bits of physical memory address.
Versatile Real-Time Executive (VRTX) is a real-time operating system developed and marketed by the company Mentor Graphics. VRTX is suitable for both traditional board-based embedded systems and SoC architectures. It has been superseded by the Nucleus RTOS.
OpenCores is a community developing digital open-source hardware through electronic design automation, with a similar ethos as the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies have been reported as adopting OpenCores IP in chips, or as adjuncts to EDA tools. OpenCores is also cited from time to time in the electronics press as an example of open source in the electronics hardware community.
The NXP ColdFire is a microprocessor that derives from the Motorola 68000 family architecture, manufactured for embedded systems development by NXP Semiconductors. It was formerly manufactured by Freescale Semiconductor which merged with NXP in 2015.
The Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit multiply–accumulates (MACs), accompanied on-chip by a microcontroller. It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.
LEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set designed by Sun Microsystems. It was originally designed by the European Space Research and Technology Centre (ESTEC), part of the European Space Agency (ESA), and after that by Gaisler Research. It is described in synthesizable VHDL. LEON has a dual license model: An LGPL/GPL FLOSS license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product. The core is configurable through VHDL generics, and is used in system-on-a-chip (SOC) designs both in research and commercial settings.
The MicroBlaze is a soft microprocessor core designed for Xilinx field-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.
A free and open-source graphics device driver is a software stack which controls computer-graphics hardware and supports graphics-rendering application programming interfaces (APIs) and is released under a free and open-source software license. Graphics device drivers are written for specific hardware to work within a specific operating system kernel and to support a range of APIs used by applications to access the graphics hardware. They may also control output to the display if the display driver is part of the graphics hardware. Most free and open-source graphics device drivers are developed by the Mesa project. The driver is made up of a compiler, a rendering API, and software which manages access to the graphics hardware.
The ETRAX CRIS is a series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993. The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token ring support has been taken out from the latest chips as it has become obsolete.
LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.
The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture.
Ingenic Semiconductor is a Chinese fabless semiconductor company based in Beijing, China founded in 2005. They purchased licenses for the MIPS architecture instruction sets in 2009 and design CPU-microarchitectures based on them. They also design system on a chip products including their CPUs and licensed semiconductor intellectual property blocks from third parties, such as Vivante Corporation, commission the fabrication of integrated circuits at semiconductor fabrication plants and sell them.
The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects.
OVPsim is a multiprocessor platform emulator used to run unchanged production binaries of the target hardware. OVPsim uses dynamic binary translation technology to achieve high simulation speeds. It has public APIs allowing users to create their own processor, peripheral and platform models. Various models are available as open source. OVPsim is a key component of the Open Virtual Platforms initiative (OVP), an organization created to promote the use of open virtual platforms for embedded software development. OVPSim requires OVP registration to download.
RISC-V is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.